| Message ID | 20231211121124.4194-1-quic_kriskura@quicinc.com |
|---|---|
| Headers | show |
| Series | Refine USB interrupt vectors on Qualcomm platforms | expand |
On 11/12/2023 13:11, Krishna Kurapati wrote: > The high speed related interrupts present on QC targets are as follows: > > dp/dm irq's > These IRQ's directly reflect changes on the DP/DM pads of the SoC. These > are used as wakeup interrupts only on SoCs with non-QUSB2 targets with > exception of SDM670/SDM845/SM6350. > > qusb2_phy irq > SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a > single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL > register. The required DPSE/DMSE configuration is done in > QUSB2PHY_INTR_CTRL register of phy address space. > > hs_phy_irq > This is completely different from the above two and is present on all > targets with exception of a few IPQ ones. The interrupt is not enabled by > default and its functionality is mutually exclusive of qusb2_phy on QUSB > targets and DP/DM on femto phy targets. > > The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" > when they should have been "qusb2_phy_irq". On Femto phy targets, the > "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", > neither of which would never be triggered directly are non-functional > currently. The implementation tries to clean up this issue by addressing > the discrepencies involved and fixing the hs_phy_irq's in respective DT's. > > Classiffy SoC's into four groups based on whether qusb2_phy interrupt > or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the > SoCs have hs_phy_irq present in them or not. > > The ss_phy_irq is optional interrupt because there are mutliple SoC's > which either support only High Speed or there are multiple controllers > within same Soc and the secondary controller is High Speed only capable. > > This breaks ABI on targets running older kernels, but since the interrupt > definitions are given wrong on many targets and to establish proper rules > for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is > necessary. This still does not explain why missing property has to be added as first one, causing huge reordering of everything here and in DTS. If pwr_event is required and we already break the ABI, reduce the impact of the change by putting it after all required interrupts. Otherwise please explain here and in commit msg why different approach is taken. Best regards, Krzysztof
On 12/13/2023 12:45 PM, Krzysztof Kozlowski wrote: > On 11/12/2023 13:11, Krishna Kurapati wrote: >> The high speed related interrupts present on QC targets are as follows: >> >> dp/dm irq's >> These IRQ's directly reflect changes on the DP/DM pads of the SoC. These >> are used as wakeup interrupts only on SoCs with non-QUSB2 targets with >> exception of SDM670/SDM845/SM6350. >> >> qusb2_phy irq >> SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a >> single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL >> register. The required DPSE/DMSE configuration is done in >> QUSB2PHY_INTR_CTRL register of phy address space. >> >> hs_phy_irq >> This is completely different from the above two and is present on all >> targets with exception of a few IPQ ones. The interrupt is not enabled by >> default and its functionality is mutually exclusive of qusb2_phy on QUSB >> targets and DP/DM on femto phy targets. >> >> The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" >> when they should have been "qusb2_phy_irq". On Femto phy targets, the >> "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", >> neither of which would never be triggered directly are non-functional >> currently. The implementation tries to clean up this issue by addressing >> the discrepencies involved and fixing the hs_phy_irq's in respective DT's. >> >> Classiffy SoC's into four groups based on whether qusb2_phy interrupt >> or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the >> SoCs have hs_phy_irq present in them or not. >> >> The ss_phy_irq is optional interrupt because there are mutliple SoC's >> which either support only High Speed or there are multiple controllers >> within same Soc and the secondary controller is High Speed only capable. >> >> This breaks ABI on targets running older kernels, but since the interrupt >> definitions are given wrong on many targets and to establish proper rules >> for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is >> necessary. > > This still does not explain why missing property has to be added as > first one, causing huge reordering of everything here and in DTS. > > If pwr_event is required and we already break the ABI, reduce the impact > of the change by putting it after all required interrupts. Otherwise > please explain here and in commit msg why different approach is taken. > Hi Krzysztof. I don't know much about the effect of the ordering on ABI. I will try to learn up on it. Would the series be good if we just move the pwr_event to the end and keep everything in v3 as it is, and push v4 for now ? Regards, Krishna,
On Wed, Dec 13, 2023 at 09:48:57PM +0530, Krishna Kurapati PSSNV wrote: > On 12/13/2023 12:45 PM, Krzysztof Kozlowski wrote: > > On 11/12/2023 13:11, Krishna Kurapati wrote: > >> The high speed related interrupts present on QC targets are as follows: > >> Classiffy SoC's into four groups based on whether qusb2_phy interrupt typo: Classify > >> or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the > >> SoCs have hs_phy_irq present in them or not. > >> > >> The ss_phy_irq is optional interrupt because there are mutliple SoC's > >> which either support only High Speed or there are multiple controllers > >> within same Soc and the secondary controller is High Speed only capable. > >> > >> This breaks ABI on targets running older kernels, but since the interrupt > >> definitions are given wrong on many targets and to establish proper rules > >> for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is > >> necessary. > > > > This still does not explain why missing property has to be added as > > first one, causing huge reordering of everything here and in DTS. > > > > If pwr_event is required and we already break the ABI, reduce the impact > > of the change by putting it after all required interrupts. Otherwise > > please explain here and in commit msg why different approach is taken. > > > > Hi Krzysztof. I don't know much about the effect of the ordering on ABI. > I will try to learn up on it. Would the series be good if we just move > the pwr_event to the end and keep everything in v3 as it is, and push v4 > for now ? Since all SoCs have the pwr_event (HS) interrupt, but not all controllers have the SS PHY interrupt, this would prevent expressing that the SS PHY is optional by keeping it last in the binding schema and making sure that minItem = maxItems - 1. And as we discussed, the aim here is to group the three classes of SoCs (qusb2, qusb2+, femto) and fix the order of these interrupts once and for all so that random reorderings, renames and omissions do not make it into the bindings next time someone grabs a downstream DT and sends it upstream. Johan
On 12/14/2023 3:26 PM, Johan Hovold wrote: > On Wed, Dec 13, 2023 at 09:48:57PM +0530, Krishna Kurapati PSSNV wrote: >> On 12/13/2023 12:45 PM, Krzysztof Kozlowski wrote: >>> On 11/12/2023 13:11, Krishna Kurapati wrote: >>>> The high speed related interrupts present on QC targets are as follows: > >>>> Classiffy SoC's into four groups based on whether qusb2_phy interrupt > > typo: Classify > >>>> or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the >>>> SoCs have hs_phy_irq present in them or not. >>>> >>>> The ss_phy_irq is optional interrupt because there are mutliple SoC's >>>> which either support only High Speed or there are multiple controllers >>>> within same Soc and the secondary controller is High Speed only capable. >>>> >>>> This breaks ABI on targets running older kernels, but since the interrupt >>>> definitions are given wrong on many targets and to establish proper rules >>>> for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is >>>> necessary. >>> >>> This still does not explain why missing property has to be added as >>> first one, causing huge reordering of everything here and in DTS. >>> >>> If pwr_event is required and we already break the ABI, reduce the impact >>> of the change by putting it after all required interrupts. Otherwise >>> please explain here and in commit msg why different approach is taken. >>> >> >> Hi Krzysztof. I don't know much about the effect of the ordering on ABI. >> I will try to learn up on it. Would the series be good if we just move >> the pwr_event to the end and keep everything in v3 as it is, and push v4 >> for now ? > > Since all SoCs have the pwr_event (HS) interrupt, but not all > controllers have the SS PHY interrupt, this would prevent expressing > that the SS PHY is optional by keeping it last in the binding schema and > making sure that minItem = maxItems - 1. > > And as we discussed, the aim here is to group the three classes of SoCs > (qusb2, qusb2+, femto) and fix the order of these interrupts once and > for all so that random reorderings, renames and omissions do not make it > into the bindings next time someone grabs a downstream DT and sends it > upstream. > Hi Krzysztof, One more reason is that all targets do have a pwr_event interrupts for sure and ss_phy is optional as Johan mentioned. So with this reasoning, can we put pwr_event first followed by others and push ss_phy to the end of list ? Regards, Krishna,
Qualcomm targets define the following interrupts for usb wakeup: {dp/dm}_hs_phy_irq, hs_phy_irq, pwr_event, ss_phy_irq. But QUSB2 Phy based targets have another interrupt which gets triggered in response to J/K states on dp/dm pads. Its functionality is replaced by dp/dm interrupts on Femto/m31/eusb2 phy based targets for wakeup purposes. Exceptions are some targets like SDM845/SDM670/SM6350 where dp/dm irq's are used although they are qusb2 phy targets. Currently in QUSB2 Phy based DT's, te qusb2_phy interrupt is named and used as "hs_phy_irq" when in fact it is a different interrupt (used by HW validation folks for debug purposes and not used on any downstream target qusb/non-qusb). On some non-QUSB2 targets (like sm8450/sm8550), the pwr_event IRQ was named as hs_phy_irq and actual pwr_event_irq was skipped. This series tries to address the discrepancies in the interrupt numbering adding the missing interrupts and correcting the existing ones. This series has been compared with downstream counter part and hw specifics to ensure the numbering is right. Since there is not functionality change the code has been only compile tested. Changes in v3: Separated out the DT changes and pushed only bindings and driver update. Modified order of irq descriptions to match them with permutations defined. Fixed nitpicks mentioned by reviewers in v2. Changes in v2: Removed additional compatibles added for different targets in v1. Specified permuations of interrupts possible for QC targets and regrouped interrupts for most of the DT's. Link to v2: https://lore.kernel.org/all/20231204100950.28712-1-quic_kriskura@quicinc.com/ Link to v1: (providing patchwork link since threading was broken in v1) https://patchwork.kernel.org/project/linux-arm-msm/cover/20231122191259.3021-1-quic_kriskura@quicinc.com/ Krishna Kurapati (2): dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings usb: dwc3: qcom: Rename hs_phy_irq to qusb2_phy_irq .../devicetree/bindings/usb/qcom,dwc3.yaml | 138 ++++++++---------- drivers/usb/dwc3/dwc3-qcom.c | 22 +-- 2 files changed, 70 insertions(+), 90 deletions(-)