| Message ID | 20231209233106.147416-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 10/12/2023 00:30, Peter Griffin wrote: > Provide dt-schema documentation for Google gs101 SoC clock controller. > Currently this adds support for cmu_top, cmu_misc and cmu_apm. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../bindings/clock/google,gs101-clock.yaml | 106 +++++ > include/dt-bindings/clock/google,gs101.h | 392 ++++++++++++++++++ > 2 files changed, 498 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > create mode 100644 include/dt-bindings/clock/google,gs101.h Wearing DT hat: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
On Sat, 09 Dec 2023 23:30:53 +0000, Peter Griffin wrote: > gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9 > where more than one pin controller can do external wake-up interrupt. > So add a dedicated compatible for it. > > Applied, thanks! [07/20] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible https://git.kernel.org/pinctrl/samsung/c/abc73e50b394f248aa8e7ecdfbd4dfa52f8e8355 Best regards,
On Sat, 09 Dec 2023 23:30:48 +0000, Peter Griffin wrote: > Provide dt-schema documentation for Google gs101 SoC clock controller. > Currently this adds support for cmu_top, cmu_misc and cmu_apm. > > Applied, thanks! [02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings https://git.kernel.org/krzk/linux/c/0a910f1606384a5886a045e36b1fc80a7fa6706b Best regards,
On 10/12/2023 00:30, Peter Griffin wrote: > Add the "google,gs101-wdt" compatible to the dt-schema documentation. > > gs101 SoC has two CPU clusters and each cluster has its own dedicated > watchdog timer (similar to exynos850 and exynosautov9 SoCs). > > These WDT instances are controlled using different bits in PMU > registers. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../devicetree/bindings/watchdog/samsung-wdt.yaml | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > index 8fb6656ba0c2..57468c2c5ece 100644 > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > @@ -17,6 +17,7 @@ description: |+ > properties: > compatible: > enum: > + - google,gs101-wdt # for Google gs101 I think you did not rebase on linux-next. The hunk differs. Best regards, Krzysztof
On 10/12/2023 00:31, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid > checkpatch --strict warnings. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Guenter, Wim, The watchdog patches are kind of independent, except that bindings has conflicting re-organization which I took via my Samsung SoC tree. If it is fine with you, please provide acks or review and I will take the watchdog changes. Best regards, Krzysztof
On 10/12/2023 00:30, Peter Griffin wrote: > Hi folks, > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > I started applying few reviewed bindings. We are getting close to end of merging time for SoC. Top-level arm/google.yaml needs ack or re-review from Rob. Best regards, Krzysztof
On Sat, Dec 9, 2023 at 5:31 PM Peter Griffin <peter.griffin@linaro.org> wrote: > > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> [snip]
On Sun, Dec 10, 2023 at 8:38 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:31, Peter Griffin wrote: > > Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 > > (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > > phones. > > > > It features: > > * 4xA55 Little cluster > > * 2xA76 Mid cluster > > * 2xX1 Big cluster > > > > ... > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > > new file mode 100644 > > index 000000000000..68b7bc47c91b > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > > @@ -0,0 +1,33 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Pinctrl binding constants for GS101 > > + * > > + * Copyright 2020-2023 Google LLC > > + */ > > + > > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > > Header guards don't really match location. > > > + > > +#define GS101_PIN_PULL_NONE 0 > > +#define GS101_PIN_PULL_DOWN 1 > > +#define GS101_PIN_PULL_UP 3 > > + > > +/* Pin function in power down mode */ > > +#define GS101_PIN_PDN_OUT0 0 > > +#define GS101_PIN_PDN_OUT1 1 > > +#define GS101_PIN_PDN_INPUT 2 > > +#define GS101_PIN_PDN_PREV 3 > > + > > +/* GS101 drive strengths */ > > +#define GS101_PIN_DRV_2_5_MA 0 > > +#define GS101_PIN_DRV_5_MA 1 > > +#define GS101_PIN_DRV_7_5_MA 2 > > +#define GS101_PIN_DRV_10_MA 3 > > + > > +#define GS101_PIN_FUNC_INPUT 0 > > +#define GS101_PIN_FUNC_OUTPUT 1 > > +#define GS101_PIN_FUNC_2 2 > > +#define GS101_PIN_FUNC_3 3 > > +#define GS101_PIN_FUNC_EINT 0xf > > + > > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > new file mode 100644 > > index 000000000000..60e112d25246 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > @@ -0,0 +1,476 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * GS101 SoC > > + * > > + * Copyright 2019-2023 Google LLC > > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > > + */ > > + > > +#include <dt-bindings/clock/google,gs101.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/soc/samsung,exynos-usi.h> > > + > > +/ { > > + compatible = "google,gs101"; > > + #address-cells = <2>; > > + #size-cells = <1>; > > + > > + interrupt-parent = <&gic>; > > + > > + aliases { > > + pinctrl0 = &pinctrl_gpio_alive; > > + pinctrl1 = &pinctrl_far_alive; > > + pinctrl2 = &pinctrl_gsacore; > > + pinctrl3 = &pinctrl_gsactrl; > > + pinctrl4 = &pinctrl_peric0; > > + pinctrl5 = &pinctrl_peric1; > > + pinctrl6 = &pinctrl_hsi1; > > + pinctrl7 = &pinctrl_hsi2; > > + }; > > + > > + pmu-0 { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; > > + }; > > + > > + pmu-1 { > > + compatible = "arm,cortex-a76-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; > > + }; > > + > > + pmu-2 { > > + compatible = "arm,cortex-x1-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; > > + }; > > + > > + pmu-3 { > > + compatible = "arm,dsu-pmu"; > > + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; > > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > > + }; > > Keep alphabetical order of top-level nodes. pmu should be before psci > > > + > > + /* TODO replace with CCF clock */ > > + dummy_clk: oscillator { > > clock-3 > > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <12345>; > > + clock-output-names = "pclk"; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + core1 { > > + cpu = <&cpu1>; > > + }; > > + core2 { > > + cpu = <&cpu2>; > > + }; > > + core3 { > > + cpu = <&cpu3>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu4>; > > + }; > > + core1 { > > + cpu = <&cpu5>; > > + }; > > + }; > > + > > + cluster2 { > > + core0 { > > + cpu = <&cpu6>; > > + }; > > + core1 { > > + cpu = <&cpu7>; > > + }; > > + }; > > + }; > > ... > > > + > > + /* ect node is required to be present by bootloader */ > > + ect { > > + }; > > alphabetical order > > > + > > + ext_24_5m: clock-1 { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-output-names = "oscclk"; > > + }; > > + > > + ext_200m: clock-2 { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-output-names = "ext-200m"; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + reserved_memory: reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + ranges; > > + > > + gsa_reserved_protected: gsa@90200000 { > > + reg = <0x0 0x90200000 0x400000>; > > + no-map; > > + }; > > + > > + tpu_fw_reserved: tpu-fw@93000000 { > > + reg = <0x0 0x93000000 0x1000000>; > > + no-map; > > + }; > > + > > + aoc_reserve: aoc@94000000 { > > + reg = <0x0 0x94000000 0x03000000>; > > + no-map; > > + }; > > + > > + abl_reserved: abl@f8800000 { > > + reg = <0x0 0xf8800000 0x02000000>; > > + no-map; > > + }; > > + > > + dss_log_reserved: dss-log-reserved@fd3f0000 { > > + reg = <0x0 0xfd3f0000 0x0000e000>; > > + no-map; > > + }; > > + > > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > > + reg = <0x0 0xfd3fe000 0x00001000>; > > + no-map; > > + }; > > + > > + bldr_log_reserved: bldr-log-reserved@fd800000 { > > + reg = <0x0 0xfd800000 0x00100000>; > > + no-map; > > + }; > > + > > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > > + reg = <0x0 0xfd900000 0x00002000>; > > + no-map; > > + }; > > + }; > > + > > + timer { > > alphabetical order, so this goes to the end > > > + compatible = "arm,armv8-timer"; > > + interrupts = > > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; > > + clock-frequency = <24576000>; > > I don't remember if you already got Marc's wrath, so just in case: are > you sure it is needed? > > Anyway, this is board specific, not SoC. > > > + }; > > + > > + soc: soc@0 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0x0 0x0 0x40000000>; > > + > > + cmu_misc: clock-controller@10010000 { > > + compatible = "google,gs101-cmu-misc"; > > + reg = <0x10010000 0x8000>; > > + #clock-cells = <1>; > > + clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, > > One space after = > > > + <&cmu_top CLK_DOUT_CMU_MISC_SSS>; > > + clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; > > + }; > > + > > + watchdog_cl0: watchdog@10060000 { > > + compatible = "google,gs101-wdt"; > > + reg = <0x10060000 0x100>; > > + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = > > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, > > Join lines (clocks = <foo bar>). Same in other places. > > > + <&ext_24_5m>; > > + clock-names = "watchdog", "watchdog_src"; > > + samsung,syscon-phandle = <&pmu_system_controller>; > > + samsung,cluster-index = <0>; > > + status = "disabled"; > > + }; > > + > > + watchdog_cl1: watchdog@10070000 { > > + compatible = "google,gs101-wdt"; > > + reg = <0x10070000 0x100>; > > + interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = > > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, > > + <&ext_24_5m>; > > + clock-names = "watchdog", "watchdog_src"; > > + samsung,syscon-phandle = <&pmu_system_controller>; > > + samsung,cluster-index = <1>; > > + status = "disabled"; > > + }; > > + > > + gic: interrupt-controller@10400000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <4>; > > + interrupt-controller; > > + reg = <0x10400000 0x10000>, /* GICD */ > > + <0x10440000 0x100000>;/* GICR * 8 */ > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > > + > > + ppi-partitions { > > + ppi_cluster0: interrupt-partition-0 { > > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > > + }; > > + > > + ppi_cluster1: interrupt-partition-1 { > > + affinity = <&cpu4 &cpu5>; > > + }; > > + > > + ppi_cluster2: interrupt-partition-2 { > > + affinity = <&cpu6 &cpu7>; > > + }; > > + }; > > + }; > > + > > + sysreg_peric0: syscon@10820000 { > > + compatible = "google,gs101-peric0-sysreg", "syscon"; > > + reg = <0x10820000 0x10000>; > > + }; > > + > > + pinctrl_peric0: pinctrl@10840000 { > > + compatible = "google,gs101-pinctrl"; > > + reg = <0x10840000 0x00001000>; > > + interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > > + }; > > + > > + usi_uart: usi@10a000c0 { > > + compatible = "google,gs101-usi", > > + "samsung,exynos850-usi"; > > + reg = <0x10a000c0 0x20>; > > + samsung,sysreg = <&sysreg_peric0 0x1020>; > > + samsung,mode = <USI_V2_UART>; > > vendor properties go to the end, after standard properties, before status. > > https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst?h=dt/next&id=0d3a771610d0e155c9aa305f142f84dda5030fae#n122 > > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + clocks = <&dummy_clk>, <&dummy_clk>; > > + clock-names = "pclk", "ipclk"; > > + status = "disabled"; > > + > > + serial_0: serial@10a00000 { > > + compatible = "google,gs101-uart"; > > + reg = <0x10a00000 0xc0>; > > + reg-io-width = <4>; > > + samsung,uart-fifosize = <256>; > > Ditto > Assuming Krzysztof's comments are fixed, feel free to add: Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > + interrupts = <GIC_SPI 634 > > + IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > > + clock-names = "uart", "clk_uart_baud0"; > > + status = "disabled"; > > + }; > > + }; > > > Best regards, > Krzysztof >
Hi Krzysztof, On Sun, 10 Dec 2023 at 14:23, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:30, Peter Griffin wrote: > > Add the "google,gs101-wdt" compatible to the dt-schema documentation. > > > > gs101 SoC has two CPU clusters and each cluster has its own dedicated > > watchdog timer (similar to exynos850 and exynosautov9 SoCs). > > > > These WDT instances are controlled using different bits in PMU > > registers. > > > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > .../devicetree/bindings/watchdog/samsung-wdt.yaml | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > > index 8fb6656ba0c2..57468c2c5ece 100644 > > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > > @@ -17,6 +17,7 @@ description: |+ > > properties: > > compatible: > > enum: > > + - google,gs101-wdt # for Google gs101 > > I think you did not rebase on linux-next. The hunk differs. It was re-based off 'next-20231130'. I will re-base off the current day's linux-next for v7. Thanks, Peter.
On Sat, 2023-12-09 at 23:30 +0000, Peter Griffin wrote: > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Cheers, André
Hi Krzysztof, Thanks for the review. On Sun, 10 Dec 2023 at 14:38, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:31, Peter Griffin wrote: > > Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 > > (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > > phones. > > > > It features: > > * 4xA55 Little cluster > > * 2xA76 Mid cluster > > * 2xX1 Big cluster > > > > ... > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > > new file mode 100644 > > index 000000000000..68b7bc47c91b > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > > @@ -0,0 +1,33 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Pinctrl binding constants for GS101 > > + * > > + * Copyright 2020-2023 Google LLC > > + */ > > + > > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > > Header guards don't really match location. Will fix. > > > + > > +#define GS101_PIN_PULL_NONE 0 > > +#define GS101_PIN_PULL_DOWN 1 > > +#define GS101_PIN_PULL_UP 3 > > + > > +/* Pin function in power down mode */ > > +#define GS101_PIN_PDN_OUT0 0 > > +#define GS101_PIN_PDN_OUT1 1 > > +#define GS101_PIN_PDN_INPUT 2 > > +#define GS101_PIN_PDN_PREV 3 > > + > > +/* GS101 drive strengths */ > > +#define GS101_PIN_DRV_2_5_MA 0 > > +#define GS101_PIN_DRV_5_MA 1 > > +#define GS101_PIN_DRV_7_5_MA 2 > > +#define GS101_PIN_DRV_10_MA 3 > > + > > +#define GS101_PIN_FUNC_INPUT 0 > > +#define GS101_PIN_FUNC_OUTPUT 1 > > +#define GS101_PIN_FUNC_2 2 > > +#define GS101_PIN_FUNC_3 3 > > +#define GS101_PIN_FUNC_EINT 0xf > > + > > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > new file mode 100644 > > index 000000000000..60e112d25246 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > @@ -0,0 +1,476 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * GS101 SoC > > + * > > + * Copyright 2019-2023 Google LLC > > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > > + */ > > + > > +#include <dt-bindings/clock/google,gs101.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/soc/samsung,exynos-usi.h> > > + > > +/ { > > + compatible = "google,gs101"; > > + #address-cells = <2>; > > + #size-cells = <1>; > > + > > + interrupt-parent = <&gic>; > > + > > + aliases { > > + pinctrl0 = &pinctrl_gpio_alive; > > + pinctrl1 = &pinctrl_far_alive; > > + pinctrl2 = &pinctrl_gsacore; > > + pinctrl3 = &pinctrl_gsactrl; > > + pinctrl4 = &pinctrl_peric0; > > + pinctrl5 = &pinctrl_peric1; > > + pinctrl6 = &pinctrl_hsi1; > > + pinctrl7 = &pinctrl_hsi2; > > + }; > > + > > + pmu-0 { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; > > + }; > > + > > + pmu-1 { > > + compatible = "arm,cortex-a76-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; > > + }; > > + > > + pmu-2 { > > + compatible = "arm,cortex-x1-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; > > + }; > > + > > + pmu-3 { > > + compatible = "arm,dsu-pmu"; > > + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; > > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > > + }; > > Keep alphabetical order of top-level nodes. pmu should be before psci Will fix > > > + > > + /* TODO replace with CCF clock */ > > + dummy_clk: oscillator { > > clock-3 Will fix > > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <12345>; > > + clock-output-names = "pclk"; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + core1 { > > + cpu = <&cpu1>; > > + }; > > + core2 { > > + cpu = <&cpu2>; > > + }; > > + core3 { > > + cpu = <&cpu3>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu4>; > > + }; > > + core1 { > > + cpu = <&cpu5>; > > + }; > > + }; > > + > > + cluster2 { > > + core0 { > > + cpu = <&cpu6>; > > + }; > > + core1 { > > + cpu = <&cpu7>; > > + }; > > + }; > > + }; > > ... > > > + > > + /* ect node is required to be present by bootloader */ > > + ect { > > + }; > > alphabetical order Will fix > > > + > > + ext_24_5m: clock-1 { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-output-names = "oscclk"; > > + }; > > + > > + ext_200m: clock-2 { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-output-names = "ext-200m"; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + reserved_memory: reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + ranges; > > + > > + gsa_reserved_protected: gsa@90200000 { > > + reg = <0x0 0x90200000 0x400000>; > > + no-map; > > + }; > > + > > + tpu_fw_reserved: tpu-fw@93000000 { > > + reg = <0x0 0x93000000 0x1000000>; > > + no-map; > > + }; > > + > > + aoc_reserve: aoc@94000000 { > > + reg = <0x0 0x94000000 0x03000000>; > > + no-map; > > + }; > > + > > + abl_reserved: abl@f8800000 { > > + reg = <0x0 0xf8800000 0x02000000>; > > + no-map; > > + }; > > + > > + dss_log_reserved: dss-log-reserved@fd3f0000 { > > + reg = <0x0 0xfd3f0000 0x0000e000>; > > + no-map; > > + }; > > + > > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > > + reg = <0x0 0xfd3fe000 0x00001000>; > > + no-map; > > + }; > > + > > + bldr_log_reserved: bldr-log-reserved@fd800000 { > > + reg = <0x0 0xfd800000 0x00100000>; > > + no-map; > > + }; > > + > > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > > + reg = <0x0 0xfd900000 0x00002000>; > > + no-map; > > + }; > > + }; > > + > > + timer { > > alphabetical order, so this goes to the end Will fix > > > + compatible = "arm,armv8-timer"; > > + interrupts = > > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; > > + clock-frequency = <24576000>; > > I don't remember if you already got Marc's wrath, so just in case: are > you sure it is needed? > > Anyway, this is board specific, not SoC. Will double check and if required move to the board file. > > > + }; > > + > > + soc: soc@0 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0x0 0x0 0x40000000>; > > + > > + cmu_misc: clock-controller@10010000 { > > + compatible = "google,gs101-cmu-misc"; > > + reg = <0x10010000 0x8000>; > > + #clock-cells = <1>; > > + clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, > > One space after = Will fix. > > > + <&cmu_top CLK_DOUT_CMU_MISC_SSS>; > > + clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; > > + }; > > + > > + watchdog_cl0: watchdog@10060000 { > > + compatible = "google,gs101-wdt"; > > + reg = <0x10060000 0x100>; > > + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = > > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, > > Join lines (clocks = <foo bar>). Same in other places. Will fix. > > > + <&ext_24_5m>; > > + clock-names = "watchdog", "watchdog_src"; > > + samsung,syscon-phandle = <&pmu_system_controller>; > > + samsung,cluster-index = <0>; > > + status = "disabled"; > > + }; > > + > > + watchdog_cl1: watchdog@10070000 { > > + compatible = "google,gs101-wdt"; > > + reg = <0x10070000 0x100>; > > + interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = > > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, > > + <&ext_24_5m>; > > + clock-names = "watchdog", "watchdog_src"; > > + samsung,syscon-phandle = <&pmu_system_controller>; > > + samsung,cluster-index = <1>; > > + status = "disabled"; > > + }; > > + > > + gic: interrupt-controller@10400000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <4>; > > + interrupt-controller; > > + reg = <0x10400000 0x10000>, /* GICD */ > > + <0x10440000 0x100000>;/* GICR * 8 */ > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > > + > > + ppi-partitions { > > + ppi_cluster0: interrupt-partition-0 { > > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > > + }; > > + > > + ppi_cluster1: interrupt-partition-1 { > > + affinity = <&cpu4 &cpu5>; > > + }; > > + > > + ppi_cluster2: interrupt-partition-2 { > > + affinity = <&cpu6 &cpu7>; > > + }; > > + }; > > + }; > > + > > + sysreg_peric0: syscon@10820000 { > > + compatible = "google,gs101-peric0-sysreg", "syscon"; > > + reg = <0x10820000 0x10000>; > > + }; > > + > > + pinctrl_peric0: pinctrl@10840000 { > > + compatible = "google,gs101-pinctrl"; > > + reg = <0x10840000 0x00001000>; > > + interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > > + }; > > + > > + usi_uart: usi@10a000c0 { > > + compatible = "google,gs101-usi", > > + "samsung,exynos850-usi"; > > + reg = <0x10a000c0 0x20>; > > + samsung,sysreg = <&sysreg_peric0 0x1020>; > > + samsung,mode = <USI_V2_UART>; > > vendor properties go to the end, after standard properties, before status. > > https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst?h=dt/next&id=0d3a771610d0e155c9aa305f142f84dda5030fae#n122 Will fix, and thanks for the pointer to the documentation about this. Much appreciated. > > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + clocks = <&dummy_clk>, <&dummy_clk>; > > + clock-names = "pclk", "ipclk"; > > + status = "disabled"; > > + > > + serial_0: serial@10a00000 { > > + compatible = "google,gs101-uart"; > > + reg = <0x10a00000 0xc0>; > > + reg-io-width = <4>; > > + samsung,uart-fifosize = <256>; > > Ditto Will fix. > > > + interrupts = <GIC_SPI 634 > > + IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > > + clock-names = "uart", "clk_uart_baud0"; > > + status = "disabled"; > > + }; > > + }; > > regards, Peter
Hi folks, This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). Thankyou to everyone who has reviewed and tested the previous series. Your time and effort doing so is much appreciated! V6 incorporates the review feedback received so far, and is rebased onto linux-next as per Krzysztof request to incorporate all his dt-binding changes for exynos. I'm really hoping V6 will be the last series, and we can get this series merged this week so it will make it into v6.8 Linux release. The main difference in v6 apart from the various nits and cosmetic changes is I have dropped support for exynos selectable analog/digital filters. I will look to progress that again after this initial series has been merged. I've also done more clock name mangling as per Sam's request to shorten the clock names, and fixed up various issues with clock parenting. As this series spans multiple subsytems the expectation is that Krzysztof will apply the whole series through the Samsung SoC tree. If the relevant subsystem maintainers can give a acked-by or reviewed-by on the relevant patches that would be most appreciated! The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven) phones. Currently DT is added for the gs101 SoC and Oriole. As you can see from the patches the SoC is based on a Samsung Exynos SoC, and therefore lots of the low level Exynos drivers and bindings can be re-used. The support added in this series consists of: * cpus * pinctrl * CCF implementation of cmu_top, cmu_misc & cmu_apm * watchdog * USI uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts Note: Booting without a dtbo works with some versions of the bootloader but crashes on others. Later versions aren't necessarily better. You can get the bootloader version with `fastboot getvar version-bootloader` Known good bootloader versions are: - - slider-1.3-11000330 - slider-1.2-9152140 Known to crash without dtbo - slider-1.3-10780582 kind regards, Peter. lore v5: https://lore.kernel.org/all/20231201160925.3136868-1-peter.griffin@linaro.org/T/ lore v4: https://lore.kernel.org/linux-arm-kernel/20231120212037.911774-1-peter.griffin@linaro.org/T/ pw v3: https://patchwork.kernel.org/project/linux-samsung-soc/cover/20231011184823.443959-1-peter.griffin@linaro.org/ lore v2: https://lore.kernel.org/all/20231010224928.2296997-1-peter.griffin@linaro.org/ lore v1: https://lore.kernel.org/linux-arm-kernel/20231005155618.700312-1-peter.griffin@linaro.org/ Changes since v5: - Collect up Reviewed-by and Tested-by tags - clk-gs101: reorder cmu_top parents in register offset order (Peter) - clk-gs101: Review cmu_top and cmu_misc parents, fix a few typos - clk-gs101: Add more name mangling to shorten DT and Linux clock name strings (Sam) - pinctrl: samsung: Drop support for digital/analog selectable filters (Peter) - Fixup cmu_top yaml example and some nitpicks (Sam) - Fixup some spelling nitpicks in google.yaml (Sam) - samsung,pinctrl-wakeup-interrupt: drop second not required google,gs101-wakeup-eint compatible (Krzysztof) - exynos-usi.yaml: add google,gs101-usi to previous enum (Krzysztof) - s3c2410_wdt: move comment, double whitespace, add BIT macro (Sam) Changes since v4: - clk-gs101: order cmu_top by register address, fix incorrect mux widths, add missing mux/div/gates (Andre) - google,gs101.h: add missing space in comment (Andre) - ckl-gs101:google,gs101.h add all remaining gates for cmu_misc and cmu_apm - update pmu dt labels (Krzysztof) - Remove uart16 rts/tx gpio definitions (Krzysztof) - Fixup various dts cosmetic nits (using consts, alignments, names) (Sam/Krzysztof) - Add more specific compatibles for arm cpu's and pmu (Sam) - Use address-cells 1 and ranges property for SoC addresses (Sam) - Encapsulate uart node in USI node (Sam) - Remove earlycon from bootargs - s3c2410_wdt: Reword QUIRK_HAS_DBGACK_BIT docs and add comment (Guenter) - s3c2410_wdt: Reorder DBGACK_MASK functionality first, gs101 SoC second (Sam/Krzysztof) Changes since v3: - Add reviewed-by and tested-by tags - google,gs101-clock.yaml: move Required to before Allof, enum for cmu*top/misc (Krzysztof) - samsung-wdt.yaml: stick to 80chars (Sam) - google.yaml - remove new line - samsung,pinctrl-wakeup-interrupt: sort alphabetically (RobH) - gs101-oriole.dts: update gpio-keys pinctrl-0 phandle for keys (Stephen) - samsung,exynos-sysreg.yaml - Alphabetical order (RobH) - pinctrl-exynos: update/move comments, slight cosmetic changes (Sam) - samsung_tty.c: update to generic drv_data name/macro (Arnd) - samsung_uart.yaml: make samsung,uart-fifosize required for gs101-uart (Arnd) - pinctrl-exynos: Remove eint irqs from alive pin controller node (Peter/Rob) - Fixup kernel test robot unused const variable warnings - clk-gs101: Update to mout_cmu_eh_bus to CLK_CON_MUX_MUX_CLKCMU_EH_BUS (Chanwoo) - clk-gs101: Update g3aa gout/dout/mout names to g3aa_g3aa for consistency (Chanwoo) - Remove .eint_gpio_init() cb on alive, alive_far, gsacore & gsactrl banks (Sam) - s3c2410_wdt: Drop windowed watchdog mode for now (Peter) - s3c2410_wdt: Separate gs101 SoC support from dbgack feature (Sam) - Move dts to arch/arm64/boot/dts/exynos/google directory (Krzysztof) Changes since v2: - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor) - Add missing windowed watchdog code (Guenter) - Fixup UART YAML bindings error (Krzysztof) - gs101.dtsi add missing serial_0 alias (me) - samsung_tty.c: fixup gs101_serial_drv_data so fifosize is obtained from DT Changes since v1: - Remove irq/gs101.h and replace macros with irq numbers globally - exynos-pmu - keep alphabetical order - add cmu_apm to clock bindings documentation - sysreg bindings - remove superfluous `google,gs101-sysreg` - watchdog bindings - Alphanumerical order, update gs201 comment - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order - samsung,pinctrl- add google,gs101-wakeup-eint compatible - clk-pll: fixup typos - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) - clk-gs101: fix alphabetical order - clk-gs101: cmu_apm: fixup typo and missing empty entry - clk-gs101: cmu_misc: remove clocks that were being registerred twice - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter - watchdog: s3c2410_wdt: remove dev_info prints - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix - gs101-oriole.dtso: Remove overlay until board_id is documented properly - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones - gpio-keys: update linux,code to use input-event-code macros - add dedicated gs101-uart compatible Peter Griffin (19): dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: serial: samsung: Add google-gs101-uart compatible dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro watchdog: s3c2410_wdt: Add support for Google gs101 SoC tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data arm64: dts: exynos: google: Add initial Google gs101 SoC support arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support MAINTAINERS: add entry for Google Tensor SoC Tudor Ambarus (1): dt-bindings: soc: samsung: usi: add google,gs101-usi compatible .../devicetree/bindings/arm/google.yaml | 53 + .../bindings/clock/google,gs101-clock.yaml | 106 + .../samsung,pinctrl-wakeup-interrupt.yaml | 1 + .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + .../bindings/serial/samsung_uart.yaml | 11 + .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../bindings/soc/samsung/exynos-usi.yaml | 1 + .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + .../bindings/watchdog/samsung-wdt.yaml | 8 +- MAINTAINERS | 10 + arch/arm64/boot/dts/exynos/Makefile | 2 + arch/arm64/boot/dts/exynos/google/Makefile | 4 + .../boot/dts/exynos/google/gs101-oriole.dts | 105 + .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1249 ++++++++ .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2512 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 6 + drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 + drivers/pinctrl/samsung/pinctrl-exynos.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + drivers/tty/serial/samsung_tty.c | 16 + drivers/watchdog/s3c2410_wdt.c | 87 +- include/dt-bindings/clock/google,gs101.h | 392 +++ 27 files changed, 5215 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/google,gs101.h