| Message ID | 1698253601-11957-1-git-send-email-quic_mojha@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 33455f8da1cf4621fc881faf0190e3671a6dc8ff |
| Headers | show |
| Series | [v2,1/4] dt-bindings: mfd: qcom,tcsr: Add compatible for sm8250/sm8350 | expand |
On Wed, 25 Oct 2023 at 20:07, Mukesh Ojha <quic_mojha@quicinc.com> wrote: > > Enable download mode for sm8250 which can help collect > ramdump for this SoC. > > Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> > --- > Changes in v2: > - Improved commit text. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index be970472f6c4..76f470a78608 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -671,6 +671,7 @@ > firmware { > scm: scm { > compatible = "qcom,scm-sm8250", "qcom,scm"; > + qcom,dload-mode = <&tcsr 0x13000>; > #reset-cells = <1>; > }; > }; > @@ -2543,6 +2544,11 @@ > #hwlock-cells = <1>; > }; > > + tcsr: syscon@1fc0000 { > + compatible = "qcom,sm8250-tcsr", "syscon"; > + reg = <0x0 0x1fc0000 0x0 0x30000>; > + }; > + > wsamacro: codec@3240000 { > compatible = "qcom,sm8250-lpass-wsa-macro"; > reg = <0 0x03240000 0 0x1000>; > -- > 2.7.4 >
On 25/10/2023 19:06, Mukesh Ojha wrote: > Document the compatible for both sm8250 and sm8350 SoCs. > > Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, 25 Oct 2023 22:36:38 +0530, Mukesh Ojha wrote: > Document the compatible for both sm8250 and sm8350 SoCs. > > Applied, thanks! [1/4] dt-bindings: mfd: qcom,tcsr: Add compatible for sm8250/sm8350 commit: a88f80580a1a076e69c4fecdf6d6441fac24e8c1 -- Lee Jones [李琼斯]
On Wed, 25 Oct 2023 22:36:38 +0530, Mukesh Ojha wrote: > Document the compatible for both sm8250 and sm8350 SoCs. > > Applied, thanks! [2/4] arm64: dts: qcom: sm8250: Add TCSR halt register space commit: d59653233e8779e3fe082eb5635b9785f2095af6 [3/4] arm64: dts: qcom: sm8350: Add TCSR halt register space commit: 1accc6031d925c6045c4776d5f3646996b0b242a [4/4] arm64: dts: qcom: sm8550: Enable download mode register write commit: 44b1f64cad5703c87918cc9ffbf9b79bb959418d Best regards,
Hi Bjorn, I have said in one of the thread here, https://lore.kernel.org/lkml/57eed7c3-e884-a28b-a1ff-e5aecbb11137@quicinc.com/ There is a wrong register offset given for sm8550 in 4/4. Since, you applied the changes in your tree, shall i send the separate patch for it, or would you mind fixing it ? -Mukesh On 12/8/2023 8:27 AM, Bjorn Andersson wrote: > > On Wed, 25 Oct 2023 22:36:38 +0530, Mukesh Ojha wrote: >> Document the compatible for both sm8250 and sm8350 SoCs. >> >> > > Applied, thanks! > > [2/4] arm64: dts: qcom: sm8250: Add TCSR halt register space > commit: d59653233e8779e3fe082eb5635b9785f2095af6 > [3/4] arm64: dts: qcom: sm8350: Add TCSR halt register space > commit: 1accc6031d925c6045c4776d5f3646996b0b242a > [4/4] arm64: dts: qcom: sm8550: Enable download mode register write > commit: 44b1f64cad5703c87918cc9ffbf9b79bb959418d > > Best regards,
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 33c3d023a106..798705ab6a46 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -29,6 +29,8 @@ properties: - qcom,sdx65-tcsr - qcom,sm4450-tcsr - qcom,sm8150-tcsr + - qcom,sm8250-tcsr + - qcom,sm8350-tcsr - qcom,sm8450-tcsr - qcom,tcsr-apq8064 - qcom,tcsr-apq8084
Document the compatible for both sm8250 and sm8350 SoCs. Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> --- Changes in v2: - Removed sm8550. - Removed regular expression from commit text/subject. Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 2 ++ 1 file changed, 2 insertions(+)