| Message ID | 20231121065006.1536-1-yongqiang.niu@mediatek.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v6] drm/mediatek: add dma buffer control for drm plane disable | expand |
Hi, Yongqiang: On Tue, 2023-11-21 at 14:50 +0800, Yongqiang Niu wrote: > the DMA buffer is released when still accessed by Mediatek display > hardware, > this flow can lead to M4U reporting a translation fault warning > > add dma buffer control flow in mediatek driver: > get dma buffer when drm plane disable > put dma buffer when overlay really disable In drm_atomic_helper_commit(), it call drm_atomic_helper_wait_for_vblanks(). And I think this would make sure that setting has been applied to hardware. So you don't need to modify mtk_plane_atomic_disable(). If there is bug in drm_atomic_helper_wait_for_vblanks(), fix drm_atomic_helper_wait_for_vblanks(). Regards, CK > > Fixes: 41016fe1028e ("drm: Rename plane->state variables in atomic > update and disable") > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 > ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_plane.c | 12 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_plane.h | 1 + > 4 files changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index c277b9fae950..188aaa97e5e3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -4,6 +4,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/dma-buf.h> > #include <linux/dma-mapping.h> > #include <linux/mailbox_controller.h> > #include <linux/of.h> > @@ -283,6 +284,23 @@ struct mtk_ddp_comp > *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > return NULL; > } > > +static void mtk_drm_dma_buf_put(struct mtk_drm_crtc *mtk_crtc) > +{ > + unsigned int i; > + > + for (i = 0; i < mtk_crtc->layer_nr; i++) { > + struct drm_plane *plane = &mtk_crtc->planes[i]; > + struct mtk_plane_state *plane_state; > + > + plane_state = to_mtk_plane_state(plane->state); > + > + if (plane_state && plane_state->pending.dma_buf) { > + dma_buf_put(plane_state->pending.dma_buf); > + plane_state->pending.dma_buf = NULL; > + } > + } > +} > + > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) > { > @@ -323,6 +341,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, > void *mssg) > mtk_crtc->pending_async_planes = false; > } > > + mtk_drm_dma_buf_put(mtk_crtc); > + > mtk_crtc->cmdq_vblank_cnt = 0; > wake_up(&mtk_crtc->cb_blocking_queue); > } > @@ -627,9 +647,14 @@ static void mtk_crtc_ddp_irq(void *data) > else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc- > >cmdq_vblank_cnt == 0) > DRM_ERROR("mtk_crtc %d CMDQ execute command > timeout!\n", > drm_crtc_index(&mtk_crtc->base)); > + > + if (!mtk_crtc->cmdq_client.chan) > + mtk_drm_dma_buf_put(mtk_crtc); > #else > if (!priv->data->shadow_register) > mtk_crtc_ddp_config(crtc, NULL); > + > + mtk_drm_dma_buf_put(mtk_crtc); > #endif > mtk_drm_finish_page_flip(mtk_crtc); > } > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 2dfaa613276a..4fd232644383 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -1019,4 +1019,5 @@ module_exit(mtk_drm_exit); > > MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); > MODULE_DESCRIPTION("Mediatek SoC DRM driver"); > +MODULE_IMPORT_NS(DMA_BUF); > MODULE_LICENSE("GPL v2"); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c > b/drivers/gpu/drm/mediatek/mtk_drm_plane.c > index ddc9355b06d5..fbfcd0d1a56c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c > @@ -12,6 +12,7 @@ > #include <drm/drm_framebuffer.h> > #include <drm/drm_gem_atomic_helper.h> > #include <linux/align.h> > +#include <linux/dma-buf.h> > > #include "mtk_drm_crtc.h" > #include "mtk_drm_ddp_comp.h" > @@ -283,6 +284,17 @@ static void mtk_plane_atomic_disable(struct > drm_plane *plane, > struct drm_plane_state *new_state = > drm_atomic_get_new_plane_state(state, > > plane); > struct mtk_plane_state *mtk_plane_state = > to_mtk_plane_state(new_state); > + struct drm_plane_state *old_state = > drm_atomic_get_old_plane_state(state, > + > plane); > + > + if (old_state && old_state->fb) { > + struct drm_gem_object *gem = old_state->fb->obj[0]; > + > + if (gem && gem->dma_buf) { > + get_dma_buf(gem->dma_buf); > + mtk_plane_state->pending.dma_buf = gem- > >dma_buf; > + } > + } > mtk_plane_state->pending.enable = false; > wmb(); /* Make sure the above parameter is set before update */ > mtk_plane_state->pending.dirty = true; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h > b/drivers/gpu/drm/mediatek/mtk_drm_plane.h > index 99aff7da0831..3aba0b58ef3c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h > @@ -33,6 +33,7 @@ struct mtk_plane_pending_state { > bool async_dirty; > bool async_config; > enum drm_color_encoding color_encoding; > + struct dma_buf *dma_buf; > }; > > struct mtk_plane_state {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index c277b9fae950..188aaa97e5e3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -4,6 +4,7 @@ */ #include <linux/clk.h> +#include <linux/dma-buf.h> #include <linux/dma-mapping.h> #include <linux/mailbox_controller.h> #include <linux/of.h> @@ -283,6 +284,23 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, return NULL; } +static void mtk_drm_dma_buf_put(struct mtk_drm_crtc *mtk_crtc) +{ + unsigned int i; + + for (i = 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *plane = &mtk_crtc->planes[i]; + struct mtk_plane_state *plane_state; + + plane_state = to_mtk_plane_state(plane->state); + + if (plane_state && plane_state->pending.dma_buf) { + dma_buf_put(plane_state->pending.dma_buf); + plane_state->pending.dma_buf = NULL; + } + } +} + #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) { @@ -323,6 +341,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) mtk_crtc->pending_async_planes = false; } + mtk_drm_dma_buf_put(mtk_crtc); + mtk_crtc->cmdq_vblank_cnt = 0; wake_up(&mtk_crtc->cb_blocking_queue); } @@ -627,9 +647,14 @@ static void mtk_crtc_ddp_irq(void *data) else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", drm_crtc_index(&mtk_crtc->base)); + + if (!mtk_crtc->cmdq_client.chan) + mtk_drm_dma_buf_put(mtk_crtc); #else if (!priv->data->shadow_register) mtk_crtc_ddp_config(crtc, NULL); + + mtk_drm_dma_buf_put(mtk_crtc); #endif mtk_drm_finish_page_flip(mtk_crtc); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 2dfaa613276a..4fd232644383 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -1019,4 +1019,5 @@ module_exit(mtk_drm_exit); MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); MODULE_DESCRIPTION("Mediatek SoC DRM driver"); +MODULE_IMPORT_NS(DMA_BUF); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index ddc9355b06d5..fbfcd0d1a56c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -12,6 +12,7 @@ #include <drm/drm_framebuffer.h> #include <drm/drm_gem_atomic_helper.h> #include <linux/align.h> +#include <linux/dma-buf.h> #include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -283,6 +284,17 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(new_state); + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); + + if (old_state && old_state->fb) { + struct drm_gem_object *gem = old_state->fb->obj[0]; + + if (gem && gem->dma_buf) { + get_dma_buf(gem->dma_buf); + mtk_plane_state->pending.dma_buf = gem->dma_buf; + } + } mtk_plane_state->pending.enable = false; wmb(); /* Make sure the above parameter is set before update */ mtk_plane_state->pending.dirty = true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 99aff7da0831..3aba0b58ef3c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -33,6 +33,7 @@ struct mtk_plane_pending_state { bool async_dirty; bool async_config; enum drm_color_encoding color_encoding; + struct dma_buf *dma_buf; }; struct mtk_plane_state {
the DMA buffer is released when still accessed by Mediatek display hardware, this flow can lead to M4U reporting a translation fault warning add dma buffer control flow in mediatek driver: get dma buffer when drm plane disable put dma buffer when overlay really disable Fixes: 41016fe1028e ("drm: Rename plane->state variables in atomic update and disable") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 12 ++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 1 + 4 files changed, 39 insertions(+)