| Message ID | 20231113174635.2540484-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 0/4] target-arm queue
Date: Mon, 13 Nov 2023 17:46:31 +0000
Message-Id: <20231113174635.2540484-1-peter.maydell@linaro.org>
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Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
Hi; here are a handful of small bug fixes for Arm guests for rc0. thanks -- PMM The following changes since commit 69680740eafa1838527c90155a7432d51b8ff203: Merge tag 'qdev-array-prop' of https://repo.or.cz/qemu/kevin into staging (2023-11-11 11:23:25 +0800) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231113 for you to fetch changes up to f6e8d1ef05a126de796ae03dd81e048e3ff48ff1: target/arm/tcg: enable PMU feature for Cortex-A8 and A9 (2023-11-13 16:31:41 +0000) ---------------------------------------------------------------- target-arm queue: * hw/arm/virt: fix GIC maintenance IRQ registration * target/arm: HVC at EL3 should go to EL3, not EL2 * target/arm: Correct MTE tag checking for reverse-copy MOPS * target/arm/tcg: enable PMU feature for Cortex-A8 and A9 ---------------------------------------------------------------- Jean-Philippe Brucker (1): hw/arm/virt: fix GIC maintenance IRQ registration Nikita Ostrenkov (1): target/arm/tcg: enable PMU feature for Cortex-A8 and A9 Peter Maydell (2): target/arm: HVC at EL3 should go to EL3, not EL2 target/arm: Correct MTE tag checking for reverse-copy MOPS hw/arm/virt.c | 6 ++++-- target/arm/tcg/cpu32.c | 2 ++ target/arm/tcg/mte_helper.c | 12 ++++++++++-- target/arm/tcg/translate-a64.c | 4 +++- 4 files changed, 19 insertions(+), 5 deletions(-)