| Message ID | 20231107024842.7650-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
Dangit, forgot the PULL tag. r~ On 11/6/23 18:48, Richard Henderson wrote: > The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8: > > Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231106 > > for you to fetch changes up to d36ce28be424385fc9f7273bf5c15ce815b5cf4e: > > tcg/sparc64: Implement tcg_out_extrl_i64_i32 (2023-11-06 10:48:46 -0800) > > ---------------------------------------------------------------- > util: Add cpuinfo for loongarch64 > tcg/loongarch64: Use cpuinfo.h > tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 > host/include/loongarch64: Add atomic16 load and store > tcg: Move expanders out of line > tcg/mips: Always implement movcond > tcg/mips: Implement neg opcodes > tcg/loongarch64: Implement neg opcodes > tcg: Make movcond and neg required opcodes > tcg: Optimize env memory operations > tcg: Canonicalize sub of immediate to add > tcg/sparc64: Implement tcg_out_extrl_i64_i32 > > ---------------------------------------------------------------- > Richard Henderson (35): > accel/tcg: Move HMP info jit and info opcount code > tcg: Add C_N2_I1 > tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 > util: Add cpuinfo for loongarch64 > tcg/loongarch64: Use cpuinfo.h > host/include/loongarch64: Add atomic16 load and store > accel/tcg: Remove redundant case in store_atom_16 > accel/tcg: Fix condition for store_atom_insert_al16 > tcg: Mark tcg_gen_op* as noinline > tcg: Move tcg_gen_op* out of line > tcg: Move generic expanders out of line > tcg: Move 32-bit expanders out of line > tcg: Move 64-bit expanders out of line > tcg: Move vec_gen_* declarations to tcg-internal.h > tcg: Move tcg_gen_opN declarations to tcg-internal.h > tcg: Unexport tcg_gen_op*_{i32,i64} > tcg: Move tcg_constant_* out of line > tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line > tcg: Move tcg_temp_free_* out of line > tcg/mips: Split out tcg_out_setcond_int > tcg/mips: Always implement movcond > tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} > tcg/mips: Implement neg opcodes > tcg/loongarch64: Implement neg opcodes > tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} > tcg: Don't free vector results > tcg/optimize: Pipe OptContext into reset_ts > tcg/optimize: Split out cmp_better_copy > tcg/optimize: Optimize env memory operations > tcg: Eliminate duplicate env store operations > tcg/optimize: Split out arg_new_constant > tcg: Canonicalize subi to addi during opcode generation > tcg/optimize: Canonicalize subi to addi during optimization > tcg/optimize: Canonicalize sub2 with constants to add2 > tcg/sparc64: Implement tcg_out_extrl_i64_i32 > > accel/tcg/internal-common.h | 2 - > host/include/loongarch64/host/atomic128-ldst.h | 52 ++ > host/include/loongarch64/host/cpuinfo.h | 21 + > .../loongarch64/host/load-extract-al16-al8.h | 39 ++ > host/include/loongarch64/host/store-insert-al16.h | 12 + > include/exec/cputlb.h | 1 - > include/tcg/tcg-op-common.h | 538 ++--------------- > include/tcg/tcg-opc.h | 8 +- > include/tcg/tcg-temp-internal.h | 56 +- > include/tcg/tcg.h | 82 --- > tcg/aarch64/tcg-target.h | 4 - > tcg/arm/tcg-target.h | 2 - > tcg/i386/tcg-target.h | 4 - > tcg/loongarch64/tcg-target-con-set.h | 2 +- > tcg/loongarch64/tcg-target.h | 12 +- > tcg/mips/tcg-target.h | 4 - > tcg/ppc/tcg-target.h | 4 - > tcg/riscv/tcg-target.h | 4 - > tcg/s390x/tcg-target.h | 4 - > tcg/sparc64/tcg-target.h | 4 - > tcg/tcg-internal.h | 18 + > tcg/tci/tcg-target.h | 4 - > accel/tcg/cputlb.c | 17 +- > accel/tcg/monitor.c | 154 +++++ > accel/tcg/translate-all.c | 127 ---- > tcg/optimize.c | 370 ++++++++++-- > tcg/tcg-op-gvec.c | 112 ++-- > tcg/tcg-op.c | 636 ++++++++++++++++----- > tcg/tcg.c | 131 ++++- > tcg/tci.c | 2 - > util/cpuinfo-loongarch.c | 35 ++ > accel/tcg/ldst_atomicity.c.inc | 14 +- > tcg/loongarch64/tcg-target.c.inc | 34 +- > tcg/mips/tcg-target.c.inc | 329 +++++------ > tcg/sparc64/tcg-target.c.inc | 5 + > util/meson.build | 2 + > 36 files changed, 1535 insertions(+), 1310 deletions(-) > create mode 100644 host/include/loongarch64/host/atomic128-ldst.h > create mode 100644 host/include/loongarch64/host/cpuinfo.h > create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h > create mode 100644 host/include/loongarch64/host/store-insert-al16.h > create mode 100644 util/cpuinfo-loongarch.c
On Tue, 7 Nov 2023 at 10:56, Richard Henderson <richard.henderson@linaro.org> wrote: > > Dangit, forgot the PULL tag. Okay, thanks for pointing it out. I've added this to the staging branch. Stefan > > r~ > > On 11/6/23 18:48, Richard Henderson wrote: > > The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8: > > > > Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800) > > > > are available in the Git repository at: > > > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231106 > > > > for you to fetch changes up to d36ce28be424385fc9f7273bf5c15ce815b5cf4e: > > > > tcg/sparc64: Implement tcg_out_extrl_i64_i32 (2023-11-06 10:48:46 -0800) > > > > ---------------------------------------------------------------- > > util: Add cpuinfo for loongarch64 > > tcg/loongarch64: Use cpuinfo.h > > tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 > > host/include/loongarch64: Add atomic16 load and store > > tcg: Move expanders out of line > > tcg/mips: Always implement movcond > > tcg/mips: Implement neg opcodes > > tcg/loongarch64: Implement neg opcodes > > tcg: Make movcond and neg required opcodes > > tcg: Optimize env memory operations > > tcg: Canonicalize sub of immediate to add > > tcg/sparc64: Implement tcg_out_extrl_i64_i32 > > > > ---------------------------------------------------------------- > > Richard Henderson (35): > > accel/tcg: Move HMP info jit and info opcount code > > tcg: Add C_N2_I1 > > tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 > > util: Add cpuinfo for loongarch64 > > tcg/loongarch64: Use cpuinfo.h > > host/include/loongarch64: Add atomic16 load and store > > accel/tcg: Remove redundant case in store_atom_16 > > accel/tcg: Fix condition for store_atom_insert_al16 > > tcg: Mark tcg_gen_op* as noinline > > tcg: Move tcg_gen_op* out of line > > tcg: Move generic expanders out of line > > tcg: Move 32-bit expanders out of line > > tcg: Move 64-bit expanders out of line > > tcg: Move vec_gen_* declarations to tcg-internal.h > > tcg: Move tcg_gen_opN declarations to tcg-internal.h > > tcg: Unexport tcg_gen_op*_{i32,i64} > > tcg: Move tcg_constant_* out of line > > tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line > > tcg: Move tcg_temp_free_* out of line > > tcg/mips: Split out tcg_out_setcond_int > > tcg/mips: Always implement movcond > > tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} > > tcg/mips: Implement neg opcodes > > tcg/loongarch64: Implement neg opcodes > > tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} > > tcg: Don't free vector results > > tcg/optimize: Pipe OptContext into reset_ts > > tcg/optimize: Split out cmp_better_copy > > tcg/optimize: Optimize env memory operations > > tcg: Eliminate duplicate env store operations > > tcg/optimize: Split out arg_new_constant > > tcg: Canonicalize subi to addi during opcode generation > > tcg/optimize: Canonicalize subi to addi during optimization > > tcg/optimize: Canonicalize sub2 with constants to add2 > > tcg/sparc64: Implement tcg_out_extrl_i64_i32 > > > > accel/tcg/internal-common.h | 2 - > > host/include/loongarch64/host/atomic128-ldst.h | 52 ++ > > host/include/loongarch64/host/cpuinfo.h | 21 + > > .../loongarch64/host/load-extract-al16-al8.h | 39 ++ > > host/include/loongarch64/host/store-insert-al16.h | 12 + > > include/exec/cputlb.h | 1 - > > include/tcg/tcg-op-common.h | 538 ++--------------- > > include/tcg/tcg-opc.h | 8 +- > > include/tcg/tcg-temp-internal.h | 56 +- > > include/tcg/tcg.h | 82 --- > > tcg/aarch64/tcg-target.h | 4 - > > tcg/arm/tcg-target.h | 2 - > > tcg/i386/tcg-target.h | 4 - > > tcg/loongarch64/tcg-target-con-set.h | 2 +- > > tcg/loongarch64/tcg-target.h | 12 +- > > tcg/mips/tcg-target.h | 4 - > > tcg/ppc/tcg-target.h | 4 - > > tcg/riscv/tcg-target.h | 4 - > > tcg/s390x/tcg-target.h | 4 - > > tcg/sparc64/tcg-target.h | 4 - > > tcg/tcg-internal.h | 18 + > > tcg/tci/tcg-target.h | 4 - > > accel/tcg/cputlb.c | 17 +- > > accel/tcg/monitor.c | 154 +++++ > > accel/tcg/translate-all.c | 127 ---- > > tcg/optimize.c | 370 ++++++++++-- > > tcg/tcg-op-gvec.c | 112 ++-- > > tcg/tcg-op.c | 636 ++++++++++++++++----- > > tcg/tcg.c | 131 ++++- > > tcg/tci.c | 2 - > > util/cpuinfo-loongarch.c | 35 ++ > > accel/tcg/ldst_atomicity.c.inc | 14 +- > > tcg/loongarch64/tcg-target.c.inc | 34 +- > > tcg/mips/tcg-target.c.inc | 329 +++++------ > > tcg/sparc64/tcg-target.c.inc | 5 + > > util/meson.build | 2 + > > 36 files changed, 1535 insertions(+), 1310 deletions(-) > > create mode 100644 host/include/loongarch64/host/atomic128-ldst.h > > create mode 100644 host/include/loongarch64/host/cpuinfo.h > > create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h > > create mode 100644 host/include/loongarch64/host/store-insert-al16.h > > create mode 100644 util/cpuinfo-loongarch.c > >
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8: Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231106 for you to fetch changes up to d36ce28be424385fc9f7273bf5c15ce815b5cf4e: tcg/sparc64: Implement tcg_out_extrl_i64_i32 (2023-11-06 10:48:46 -0800) ---------------------------------------------------------------- util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 host/include/loongarch64: Add atomic16 load and store tcg: Move expanders out of line tcg/mips: Always implement movcond tcg/mips: Implement neg opcodes tcg/loongarch64: Implement neg opcodes tcg: Make movcond and neg required opcodes tcg: Optimize env memory operations tcg: Canonicalize sub of immediate to add tcg/sparc64: Implement tcg_out_extrl_i64_i32 ---------------------------------------------------------------- Richard Henderson (35): accel/tcg: Move HMP info jit and info opcount code tcg: Add C_N2_I1 tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h host/include/loongarch64: Add atomic16 load and store accel/tcg: Remove redundant case in store_atom_16 accel/tcg: Fix condition for store_atom_insert_al16 tcg: Mark tcg_gen_op* as noinline tcg: Move tcg_gen_op* out of line tcg: Move generic expanders out of line tcg: Move 32-bit expanders out of line tcg: Move 64-bit expanders out of line tcg: Move vec_gen_* declarations to tcg-internal.h tcg: Move tcg_gen_opN declarations to tcg-internal.h tcg: Unexport tcg_gen_op*_{i32,i64} tcg: Move tcg_constant_* out of line tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line tcg: Move tcg_temp_free_* out of line tcg/mips: Split out tcg_out_setcond_int tcg/mips: Always implement movcond tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} tcg/mips: Implement neg opcodes tcg/loongarch64: Implement neg opcodes tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} tcg: Don't free vector results tcg/optimize: Pipe OptContext into reset_ts tcg/optimize: Split out cmp_better_copy tcg/optimize: Optimize env memory operations tcg: Eliminate duplicate env store operations tcg/optimize: Split out arg_new_constant tcg: Canonicalize subi to addi during opcode generation tcg/optimize: Canonicalize subi to addi during optimization tcg/optimize: Canonicalize sub2 with constants to add2 tcg/sparc64: Implement tcg_out_extrl_i64_i32 accel/tcg/internal-common.h | 2 - host/include/loongarch64/host/atomic128-ldst.h | 52 ++ host/include/loongarch64/host/cpuinfo.h | 21 + .../loongarch64/host/load-extract-al16-al8.h | 39 ++ host/include/loongarch64/host/store-insert-al16.h | 12 + include/exec/cputlb.h | 1 - include/tcg/tcg-op-common.h | 538 ++--------------- include/tcg/tcg-opc.h | 8 +- include/tcg/tcg-temp-internal.h | 56 +- include/tcg/tcg.h | 82 --- tcg/aarch64/tcg-target.h | 4 - tcg/arm/tcg-target.h | 2 - tcg/i386/tcg-target.h | 4 - tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/loongarch64/tcg-target.h | 12 +- tcg/mips/tcg-target.h | 4 - tcg/ppc/tcg-target.h | 4 - tcg/riscv/tcg-target.h | 4 - tcg/s390x/tcg-target.h | 4 - tcg/sparc64/tcg-target.h | 4 - tcg/tcg-internal.h | 18 + tcg/tci/tcg-target.h | 4 - accel/tcg/cputlb.c | 17 +- accel/tcg/monitor.c | 154 +++++ accel/tcg/translate-all.c | 127 ---- tcg/optimize.c | 370 ++++++++++-- tcg/tcg-op-gvec.c | 112 ++-- tcg/tcg-op.c | 636 ++++++++++++++++----- tcg/tcg.c | 131 ++++- tcg/tci.c | 2 - util/cpuinfo-loongarch.c | 35 ++ accel/tcg/ldst_atomicity.c.inc | 14 +- tcg/loongarch64/tcg-target.c.inc | 34 +- tcg/mips/tcg-target.c.inc | 329 +++++------ tcg/sparc64/tcg-target.c.inc | 5 + util/meson.build | 2 + 36 files changed, 1535 insertions(+), 1310 deletions(-) create mode 100644 host/include/loongarch64/host/atomic128-ldst.h create mode 100644 host/include/loongarch64/host/cpuinfo.h create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h create mode 100644 host/include/loongarch64/host/store-insert-al16.h create mode 100644 util/cpuinfo-loongarch.c