| Message ID | 20231027143942.3413881-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote: > > Hi; here's the latest target-arm queue. Mostly this is refactoring > and cleanup type patches. > > thanks > -- PMM Hi Peter, I can't find this email thread on lore.kernel.org and your git repo doesn't let me fetch the tag: $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 fatal: couldn't find remote ref tags/pull-target-arm-20231027 cgit shows the tag though, for some reason: https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027 Any idea what's up with this pull request? Thanks! Stefan > > The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be: > > Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 > > for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229: > > hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Correct minor errors in Cortex-A710 definition > * Implement Neoverse N2 CPU model > * Refactor feature test functions out into separate header > * Fix syndrome for FGT traps on ERET > * Remove 'hw/arm/boot.h' includes from various header files > * pxa2xx: Refactoring/cleanup > * Avoid using 'first_cpu' when first ARM CPU is reachable > * misc/led: LED state is set opposite of what is expected > * hw/net/cadence_gen: clean up to use FIELD macros > * hw/net/cadence_gem: perform PHY access on write only > * hw/net/cadence_gem: enforce 32 bits variable size for CRC > > ---------------------------------------------------------------- > Glenn Miles (1): > misc/led: LED state is set opposite of what is expected > > Luc Michel (11): > hw/net/cadence_gem: use REG32 macro for register definitions > hw/net/cadence_gem: use FIELD for screening registers > hw/net/cadence_gem: use FIELD to describe NWCTRL register fields > hw/net/cadence_gem: use FIELD to describe NWCFG register fields > hw/net/cadence_gem: use FIELD to describe DMACFG register fields > hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields > hw/net/cadence_gem: use FIELD to describe IRQ register fields > hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields > hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields > hw/net/cadence_gem: perform PHY access on write only > hw/net/cadence_gem: enforce 32 bits variable size for CRC > > Peter Maydell (9): > target/arm: Correct minor errors in Cortex-A710 definition > target/arm: Implement Neoverse N2 CPU model > target/arm: Move feature test functions to their own header > target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together > target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 > target/arm: Move ID_AA64ISAR* test functions together > target/arm: Move ID_AA64PFR* tests together > target/arm: Move ID_AA64DFR* feature tests together > target/arm: Fix syndrome for FGT traps on ERET > > Philippe Mathieu-Daudé (20): > hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header > hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header > hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header > hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header > hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header > hw/sd/pxa2xx: Realize sysbus device before accessing it > hw/sd/pxa2xx: Do not open-code sysbus_create_simple() > hw/pcmcia/pxa2xx: Realize sysbus device before accessing it > hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple() > hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() > hw/intc/pxa2xx: Convert to Resettable interface > hw/intc/pxa2xx: Pass CPU reference using QOM link property > hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init() > hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it > hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable > > docs/system/arm/virt.rst | 1 + > bsd-user/arm/target_arch.h | 1 + > include/hw/arm/allwinner-a10.h | 1 - > include/hw/arm/allwinner-h3.h | 1 - > include/hw/arm/allwinner-r40.h | 1 - > include/hw/arm/fsl-imx25.h | 1 - > include/hw/arm/fsl-imx31.h | 1 - > include/hw/arm/fsl-imx6.h | 1 - > include/hw/arm/fsl-imx6ul.h | 1 - > include/hw/arm/fsl-imx7.h | 1 - > include/hw/arm/pxa.h | 2 - > include/hw/arm/xlnx-versal.h | 1 - > include/hw/arm/xlnx-zynqmp.h | 1 - > linux-user/aarch64/target_prctl.h | 2 + > target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++ > target/arm/cpu.h | 971 ------------------------------------- > target/arm/internals.h | 1 + > target/arm/tcg/translate.h | 2 +- > hw/arm/armv7m.c | 1 + > hw/arm/bananapi_m2u.c | 3 +- > hw/arm/cubieboard.c | 1 + > hw/arm/exynos4_boards.c | 7 +- > hw/arm/imx25_pdk.c | 1 + > hw/arm/kzm.c | 1 + > hw/arm/mcimx6ul-evk.c | 1 + > hw/arm/mcimx7d-sabre.c | 1 + > hw/arm/orangepi.c | 3 +- > hw/arm/pxa2xx.c | 17 +- > hw/arm/pxa2xx_pic.c | 38 +- > hw/arm/realview.c | 2 +- > hw/arm/sabrelite.c | 1 + > hw/arm/sbsa-ref.c | 1 + > hw/arm/virt.c | 1 + > hw/arm/xilinx_zynq.c | 2 +- > hw/arm/xlnx-versal-virt.c | 1 + > hw/arm/xlnx-zcu102.c | 1 + > hw/intc/armv7m_nvic.c | 1 + > hw/misc/led.c | 2 +- > hw/net/cadence_gem.c | 884 ++++++++++++++++++--------------- > hw/pcmcia/pxa2xx.c | 15 - > hw/sd/pxa2xx_mmci.c | 7 +- > linux-user/aarch64/cpu_loop.c | 1 + > linux-user/aarch64/signal.c | 1 + > linux-user/arm/signal.c | 1 + > linux-user/elfload.c | 4 + > linux-user/mmap.c | 4 + > target/arm/arch_dump.c | 1 + > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 1 + > target/arm/debug_helper.c | 1 + > target/arm/gdbstub.c | 1 + > target/arm/helper.c | 1 + > target/arm/kvm64.c | 1 + > target/arm/machine.c | 1 + > target/arm/ptw.c | 1 + > target/arm/tcg/cpu64.c | 115 ++++- > target/arm/tcg/hflags.c | 1 + > target/arm/tcg/m_helper.c | 1 + > target/arm/tcg/op_helper.c | 1 + > target/arm/tcg/pauth_helper.c | 1 + > target/arm/tcg/tlb_helper.c | 1 + > target/arm/tcg/translate-a64.c | 4 +- > target/arm/vfp_helper.c | 1 + > 63 files changed, 1702 insertions(+), 1419 deletions(-) > create mode 100644 target/arm/cpu-features.h >
On Sun, 29 Oct 2023 at 23:15, Stefan Hajnoczi <stefanha@gmail.com> wrote: > > On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote: > > > > Hi; here's the latest target-arm queue. Mostly this is refactoring > > and cleanup type patches. > Hi Peter, > I can't find this email thread on lore.kernel.org and your git repo > doesn't let me fetch the tag: > > $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20231027 > fatal: couldn't find remote ref tags/pull-target-arm-20231027 This works for me: $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 remote: Enumerating objects: 16753, done. remote: Counting objects: 100% (16753/16753), done. remote: Compressing objects: 100% (3181/3181), done. remote: Total 17529 (delta 14031), reused 16255 (delta 13541), pack-reused 776 Receiving objects: 100% (17529/17529), 22.87 MiB | 10.44 MiB/s, done. Resolving deltas: 100% (14498/14498), completed with 1672 local objects. From https://git.linaro.org/people/pmaydell/qemu-arm * tag pull-target-arm-20231027 -> FETCH_HEAD > cgit shows the tag though, for some reason: > https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027 > > Any idea what's up with this pull request? Thanks! 'git.linaro.org' has several geolocated servers and pushes to it should get mirrored across to all of them. Maybe the syncing between them went wrong? You could try using one specific one: https://git-us.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 git-ie.linaro.org also seems to have the tag. If you let me know what 'git.linaro.org' resolves to for you I can check with our IT whether the syncing has broken. I don't know why the email hasn't hit lore.kernel.org, but that seems likely to be a problem with lore, because the series did reach patchew, the lists.gnu.org archive, and you: https://patchew.org/QEMU/20231027143942.3413881-1-peter.maydell@linaro.org/ https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg09548.html thanks -- PMM
On Mon, 30 Oct 2023 at 19:09, Peter Maydell <peter.maydell@linaro.org> wrote: > > On Sun, 29 Oct 2023 at 23:15, Stefan Hajnoczi <stefanha@gmail.com> wrote: > > > > On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote: > > > > > > Hi; here's the latest target-arm queue. Mostly this is refactoring > > > and cleanup type patches. > > > Hi Peter, > > I can't find this email thread on lore.kernel.org and your git repo > > doesn't let me fetch the tag: > > > > $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git > > tags/pull-target-arm-20231027 > > fatal: couldn't find remote ref tags/pull-target-arm-20231027 > > This works for me: > > $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20231027 > remote: Enumerating objects: 16753, done. > remote: Counting objects: 100% (16753/16753), done. > remote: Compressing objects: 100% (3181/3181), done. > remote: Total 17529 (delta 14031), reused 16255 (delta 13541), pack-reused 776 > Receiving objects: 100% (17529/17529), 22.87 MiB | 10.44 MiB/s, done. > Resolving deltas: 100% (14498/14498), completed with 1672 local objects. > From https://git.linaro.org/people/pmaydell/qemu-arm > * tag pull-target-arm-20231027 -> FETCH_HEAD > > > cgit shows the tag though, for some reason: > > https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027 > > > > Any idea what's up with this pull request? Thanks! > > 'git.linaro.org' has several geolocated servers and pushes to > it should get mirrored across to all of them. Maybe the > syncing between them went wrong? You could try using one > specific one: > https://git-us.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20231027 > > git-ie.linaro.org also seems to have the tag. Yes, that solves the problem. DNS was resolving to git-ap.linaro.org for me and it doesn't have the tag. Thanks, Stefan
On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote: > > Hi; here's the latest target-arm queue. Mostly this is refactoring > and cleanup type patches. Applied, thanks! Stefan > > thanks > -- PMM > > The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be: > > Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 > > for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229: > > hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Correct minor errors in Cortex-A710 definition > * Implement Neoverse N2 CPU model > * Refactor feature test functions out into separate header > * Fix syndrome for FGT traps on ERET > * Remove 'hw/arm/boot.h' includes from various header files > * pxa2xx: Refactoring/cleanup > * Avoid using 'first_cpu' when first ARM CPU is reachable > * misc/led: LED state is set opposite of what is expected > * hw/net/cadence_gen: clean up to use FIELD macros > * hw/net/cadence_gem: perform PHY access on write only > * hw/net/cadence_gem: enforce 32 bits variable size for CRC > > ---------------------------------------------------------------- > Glenn Miles (1): > misc/led: LED state is set opposite of what is expected > > Luc Michel (11): > hw/net/cadence_gem: use REG32 macro for register definitions > hw/net/cadence_gem: use FIELD for screening registers > hw/net/cadence_gem: use FIELD to describe NWCTRL register fields > hw/net/cadence_gem: use FIELD to describe NWCFG register fields > hw/net/cadence_gem: use FIELD to describe DMACFG register fields > hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields > hw/net/cadence_gem: use FIELD to describe IRQ register fields > hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields > hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields > hw/net/cadence_gem: perform PHY access on write only > hw/net/cadence_gem: enforce 32 bits variable size for CRC > > Peter Maydell (9): > target/arm: Correct minor errors in Cortex-A710 definition > target/arm: Implement Neoverse N2 CPU model > target/arm: Move feature test functions to their own header > target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together > target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 > target/arm: Move ID_AA64ISAR* test functions together > target/arm: Move ID_AA64PFR* tests together > target/arm: Move ID_AA64DFR* feature tests together > target/arm: Fix syndrome for FGT traps on ERET > > Philippe Mathieu-Daudé (20): > hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header > hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header > hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header > hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header > hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header > hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header > hw/sd/pxa2xx: Realize sysbus device before accessing it > hw/sd/pxa2xx: Do not open-code sysbus_create_simple() > hw/pcmcia/pxa2xx: Realize sysbus device before accessing it > hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple() > hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() > hw/intc/pxa2xx: Convert to Resettable interface > hw/intc/pxa2xx: Pass CPU reference using QOM link property > hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init() > hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it > hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable > > docs/system/arm/virt.rst | 1 + > bsd-user/arm/target_arch.h | 1 + > include/hw/arm/allwinner-a10.h | 1 - > include/hw/arm/allwinner-h3.h | 1 - > include/hw/arm/allwinner-r40.h | 1 - > include/hw/arm/fsl-imx25.h | 1 - > include/hw/arm/fsl-imx31.h | 1 - > include/hw/arm/fsl-imx6.h | 1 - > include/hw/arm/fsl-imx6ul.h | 1 - > include/hw/arm/fsl-imx7.h | 1 - > include/hw/arm/pxa.h | 2 - > include/hw/arm/xlnx-versal.h | 1 - > include/hw/arm/xlnx-zynqmp.h | 1 - > linux-user/aarch64/target_prctl.h | 2 + > target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++ > target/arm/cpu.h | 971 ------------------------------------- > target/arm/internals.h | 1 + > target/arm/tcg/translate.h | 2 +- > hw/arm/armv7m.c | 1 + > hw/arm/bananapi_m2u.c | 3 +- > hw/arm/cubieboard.c | 1 + > hw/arm/exynos4_boards.c | 7 +- > hw/arm/imx25_pdk.c | 1 + > hw/arm/kzm.c | 1 + > hw/arm/mcimx6ul-evk.c | 1 + > hw/arm/mcimx7d-sabre.c | 1 + > hw/arm/orangepi.c | 3 +- > hw/arm/pxa2xx.c | 17 +- > hw/arm/pxa2xx_pic.c | 38 +- > hw/arm/realview.c | 2 +- > hw/arm/sabrelite.c | 1 + > hw/arm/sbsa-ref.c | 1 + > hw/arm/virt.c | 1 + > hw/arm/xilinx_zynq.c | 2 +- > hw/arm/xlnx-versal-virt.c | 1 + > hw/arm/xlnx-zcu102.c | 1 + > hw/intc/armv7m_nvic.c | 1 + > hw/misc/led.c | 2 +- > hw/net/cadence_gem.c | 884 ++++++++++++++++++--------------- > hw/pcmcia/pxa2xx.c | 15 - > hw/sd/pxa2xx_mmci.c | 7 +- > linux-user/aarch64/cpu_loop.c | 1 + > linux-user/aarch64/signal.c | 1 + > linux-user/arm/signal.c | 1 + > linux-user/elfload.c | 4 + > linux-user/mmap.c | 4 + > target/arm/arch_dump.c | 1 + > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 1 + > target/arm/debug_helper.c | 1 + > target/arm/gdbstub.c | 1 + > target/arm/helper.c | 1 + > target/arm/kvm64.c | 1 + > target/arm/machine.c | 1 + > target/arm/ptw.c | 1 + > target/arm/tcg/cpu64.c | 115 ++++- > target/arm/tcg/hflags.c | 1 + > target/arm/tcg/m_helper.c | 1 + > target/arm/tcg/op_helper.c | 1 + > target/arm/tcg/pauth_helper.c | 1 + > target/arm/tcg/tlb_helper.c | 1 + > target/arm/tcg/translate-a64.c | 4 +- > target/arm/vfp_helper.c | 1 + > 63 files changed, 1702 insertions(+), 1419 deletions(-) > create mode 100644 target/arm/cpu-features.h >
On Mon, 30 Oct 2023 at 22:09, Stefan Hajnoczi <stefanha@gmail.com> wrote: > > On Mon, 30 Oct 2023 at 19:09, Peter Maydell <peter.maydell@linaro.org> wrote: > > 'git.linaro.org' has several geolocated servers and pushes to > > it should get mirrored across to all of them. Maybe the > > syncing between them went wrong? You could try using one > > specific one: > > https://git-us.linaro.org/people/pmaydell/qemu-arm.git > > tags/pull-target-arm-20231027 > > > > git-ie.linaro.org also seems to have the tag. > > Yes, that solves the problem. DNS was resolving to git-ap.linaro.org > for me and it doesn't have the tag. This was a problem with that specific mirror server; it has been resolved, and future pulls with 'git.linaro.org' should work as usual. thanks -- PMM
Hi; here's the latest target-arm queue. Mostly this is refactoring and cleanup type patches. thanks -- PMM The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be: Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027 for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229: hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100) ---------------------------------------------------------------- target-arm queue: * Correct minor errors in Cortex-A710 definition * Implement Neoverse N2 CPU model * Refactor feature test functions out into separate header * Fix syndrome for FGT traps on ERET * Remove 'hw/arm/boot.h' includes from various header files * pxa2xx: Refactoring/cleanup * Avoid using 'first_cpu' when first ARM CPU is reachable * misc/led: LED state is set opposite of what is expected * hw/net/cadence_gen: clean up to use FIELD macros * hw/net/cadence_gem: perform PHY access on write only * hw/net/cadence_gem: enforce 32 bits variable size for CRC ---------------------------------------------------------------- Glenn Miles (1): misc/led: LED state is set opposite of what is expected Luc Michel (11): hw/net/cadence_gem: use REG32 macro for register definitions hw/net/cadence_gem: use FIELD for screening registers hw/net/cadence_gem: use FIELD to describe NWCTRL register fields hw/net/cadence_gem: use FIELD to describe NWCFG register fields hw/net/cadence_gem: use FIELD to describe DMACFG register fields hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields hw/net/cadence_gem: use FIELD to describe IRQ register fields hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields hw/net/cadence_gem: perform PHY access on write only hw/net/cadence_gem: enforce 32 bits variable size for CRC Peter Maydell (9): target/arm: Correct minor errors in Cortex-A710 definition target/arm: Implement Neoverse N2 CPU model target/arm: Move feature test functions to their own header target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 target/arm: Move ID_AA64ISAR* test functions together target/arm: Move ID_AA64PFR* tests together target/arm: Move ID_AA64DFR* feature tests together target/arm: Fix syndrome for FGT traps on ERET Philippe Mathieu-Daudé (20): hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header hw/sd/pxa2xx: Realize sysbus device before accessing it hw/sd/pxa2xx: Do not open-code sysbus_create_simple() hw/pcmcia/pxa2xx: Realize sysbus device before accessing it hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple() hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() hw/intc/pxa2xx: Convert to Resettable interface hw/intc/pxa2xx: Pass CPU reference using QOM link property hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init() hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable docs/system/arm/virt.rst | 1 + bsd-user/arm/target_arch.h | 1 + include/hw/arm/allwinner-a10.h | 1 - include/hw/arm/allwinner-h3.h | 1 - include/hw/arm/allwinner-r40.h | 1 - include/hw/arm/fsl-imx25.h | 1 - include/hw/arm/fsl-imx31.h | 1 - include/hw/arm/fsl-imx6.h | 1 - include/hw/arm/fsl-imx6ul.h | 1 - include/hw/arm/fsl-imx7.h | 1 - include/hw/arm/pxa.h | 2 - include/hw/arm/xlnx-versal.h | 1 - include/hw/arm/xlnx-zynqmp.h | 1 - linux-user/aarch64/target_prctl.h | 2 + target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 971 ------------------------------------- target/arm/internals.h | 1 + target/arm/tcg/translate.h | 2 +- hw/arm/armv7m.c | 1 + hw/arm/bananapi_m2u.c | 3 +- hw/arm/cubieboard.c | 1 + hw/arm/exynos4_boards.c | 7 +- hw/arm/imx25_pdk.c | 1 + hw/arm/kzm.c | 1 + hw/arm/mcimx6ul-evk.c | 1 + hw/arm/mcimx7d-sabre.c | 1 + hw/arm/orangepi.c | 3 +- hw/arm/pxa2xx.c | 17 +- hw/arm/pxa2xx_pic.c | 38 +- hw/arm/realview.c | 2 +- hw/arm/sabrelite.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + hw/arm/xilinx_zynq.c | 2 +- hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 1 + hw/intc/armv7m_nvic.c | 1 + hw/misc/led.c | 2 +- hw/net/cadence_gem.c | 884 ++++++++++++++++++--------------- hw/pcmcia/pxa2xx.c | 15 - hw/sd/pxa2xx_mmci.c | 7 +- linux-user/aarch64/cpu_loop.c | 1 + linux-user/aarch64/signal.c | 1 + linux-user/arm/signal.c | 1 + linux-user/elfload.c | 4 + linux-user/mmap.c | 4 + target/arm/arch_dump.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 1 + target/arm/gdbstub.c | 1 + target/arm/helper.c | 1 + target/arm/kvm64.c | 1 + target/arm/machine.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/cpu64.c | 115 ++++- target/arm/tcg/hflags.c | 1 + target/arm/tcg/m_helper.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/pauth_helper.c | 1 + target/arm/tcg/tlb_helper.c | 1 + target/arm/tcg/translate-a64.c | 4 +- target/arm/vfp_helper.c | 1 + 63 files changed, 1702 insertions(+), 1419 deletions(-) create mode 100644 target/arm/cpu-features.h