| Message ID | 20231013140116.255-1-philmd@linaro.org |
|---|---|
| Headers | show |
| Series | target: Make 'cpu-qom.h' really target agnostic | expand |
Hi Philippe, On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote: > Date: Fri, 13 Oct 2023 16:00:59 +0200 > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic > X-Mailer: git-send-email 2.41.0 > > Since v1: > - Added R-b tags > - Addressed Richard comments > - Postponed OBJECT_DECLARE_CPU_TYPE() changes > > A heterogeneous machine must be able to instantiate CPUs > from different architectures. Does this mean the different ISA cores in heterogeneous machine? And is this case for TCG? > In order to do that, the > common hw/ code has to access to the QOM CPU definitions > from various architecture. About this kind of heterogeneous machine with multiple CPUs, is there any initial configuration command line example? I'm not sure how to configure this case...The main unsure thing is whether the configuration is based on the granularity of the CPU (by "-cpu") or the granularity of the core device (by "-device xxx-core"). -Zhao > > Those QOM definitions are published in "target/foo/cpu-qom.h". > All 'cpu-qom.h' must be target agnostic, so hw/ can include > multiple of them in order to create a heterogeneous machine. > > This series strengthen all (except PPC...) target 'cpu-qom.h', > making them target agnostic. > > For various targets it is just a matter of moving definitions > where they belong (either 'cpu.h' or 'cpu-qom.h'). > > For few (mips/riscv/sparc/x86) we have to remove the target > specific definitions (which 'taint' the header as target specific). > > For mips/sparc/x86 this implies splitting the base target > definition by making it explicit to the build type (32 or 64-bit). > > PPC is missing because CPU types are currently registered > indistinctly, and whether a CPU is 32/64 bit can not be detected > at build time (it is done in each cpu_class_init() handler, > *after* the type is registered). > > Based-on: <20231010074952.79165-1-philmd@linaro.org> > Introduce qtest_get_base_arch() / qtest_get_arch_bits() > > Philippe Mathieu-Daudé (16): > target: Unify QOM style > target: Mention 'cpu-qom.h' is target agnostic > target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h' > target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' > target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' > target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' > target/hexagon: Declare QOM definitions in 'cpu-qom.h' > target/loongarch: Declare QOM definitions in 'cpu-qom.h' > target/nios2: Declare QOM definitions in 'cpu-qom.h' > target/openrisc: Declare QOM definitions in 'cpu-qom.h' > target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h' > target: Move ArchCPUClass definition to 'cpu.h' > target/i386: Declare CPU QOM types using DEFINE_TYPES() macro > target/mips: Declare CPU QOM types using DEFINE_TYPES() macro > target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro > target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro > > target/alpha/cpu-qom.h | 21 ++----------- > target/alpha/cpu.h | 17 ++++++++--- > target/arm/cpu-qom.h | 61 +------------------------------------ > target/arm/cpu.h | 55 +++++++++++++++++++++++++++++++-- > target/avr/cpu-qom.h | 20 ++---------- > target/avr/cpu.h | 18 ++++++++--- > target/cris/cpu-qom.h | 24 ++------------- > target/cris/cpu.h | 20 +++++++++--- > target/hexagon/cpu-qom.h | 27 ++++++++++++++++ > target/hexagon/cpu.h | 20 ++---------- > target/hppa/cpu-qom.h | 20 +----------- > target/hppa/cpu.h | 16 ++++++++-- > target/i386/cpu-qom.h | 42 ++----------------------- > target/i386/cpu.h | 39 +++++++++++++++++++++--- > target/loongarch/cpu-qom.h | 23 ++++++++++++++ > target/loongarch/cpu.h | 14 +-------- > target/m68k/cpu-qom.h | 21 ++----------- > target/m68k/cpu.h | 17 ++++++++--- > target/microblaze/cpu-qom.h | 20 +----------- > target/microblaze/cpu.h | 15 +++++++-- > target/mips/cpu-qom.h | 23 ++------------ > target/mips/cpu.h | 21 ++++++++++--- > target/nios2/cpu-qom.h | 18 +++++++++++ > target/nios2/cpu.h | 11 +------ > target/openrisc/cpu-qom.h | 21 +++++++++++++ > target/openrisc/cpu.h | 14 +-------- > target/ppc/cpu-qom.h | 3 +- > target/ppc/cpu.h | 4 +-- > target/riscv/cpu-qom.h | 26 ++-------------- > target/riscv/cpu.h | 24 +++++++++++++-- > target/rx/cpu-qom.h | 20 ++---------- > target/rx/cpu.h | 18 ++++++++--- > target/s390x/cpu-qom.h | 41 +++---------------------- > target/s390x/cpu.h | 34 ++++++++++++++++++--- > target/s390x/cpu_models.h | 8 ++--- > target/sh4/cpu-qom.h | 28 ++--------------- > target/sh4/cpu.h | 24 ++++++++++++--- > target/sparc/cpu-qom.h | 23 ++------------ > target/sparc/cpu.h | 22 +++++++++---- > target/tricore/cpu-qom.h | 15 +++------ > target/tricore/cpu.h | 10 +++--- > target/xtensa/cpu-qom.h | 26 ++-------------- > target/xtensa/cpu.h | 24 +++++++++++---- > target/i386/cpu.c | 50 ++++++++++++++---------------- > target/mips/cpu.c | 23 ++++++++------ > target/ppc/cpu_init.c | 52 ++++++++++++++----------------- > target/sparc/cpu.c | 23 ++++++++------ > 47 files changed, 528 insertions(+), 588 deletions(-) > create mode 100644 target/hexagon/cpu-qom.h > create mode 100644 target/loongarch/cpu-qom.h > create mode 100644 target/nios2/cpu-qom.h > create mode 100644 target/openrisc/cpu-qom.h > > -- > 2.41.0 >
Hi Zhao, On 20/10/23 07:50, Zhao Liu wrote: > Hi Philippe, > > On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote: >> Date: Fri, 13 Oct 2023 16:00:59 +0200 >> From: Philippe Mathieu-Daudé <philmd@linaro.org> >> Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic >> X-Mailer: git-send-email 2.41.0 >> >> Since v1: >> - Added R-b tags >> - Addressed Richard comments >> - Postponed OBJECT_DECLARE_CPU_TYPE() changes >> >> A heterogeneous machine must be able to instantiate CPUs >> from different architectures. > > Does this mean the different ISA cores in heterogeneous machine? Yes. Currently the ARM target already allows you to do that (multiple ISA cores within the same architecture), see the xlnx-zcu102 and fby35 machines. > And is this case for TCG? This is *only* for TCG. I expect hardware accel + TCG to be theoretically possible, but no interest has been shown for it. Anyhow this requires heterogeneous TCG as a first step. >> In order to do that, the >> common hw/ code has to access to the QOM CPU definitions >> from various architecture. > > About this kind of heterogeneous machine with multiple CPUs, is there > any initial configuration command line example? I'm prototyping in plain C but our plan is to start with a QMP prototype. Command line configuration is not an option, we decided to ignore it. I'll describe that better in a RFC document I should post soon. Regards, Phil. > I'm not sure how to configure this case...The main unsure thing is > whether the configuration is based on the granularity of the CPU > (by "-cpu") or the granularity of the core device (by "-device > xxx-core"). > > -Zhao
Hi Philippe, On Fri, Oct 20, 2023 at 01:30:50PM +0200, Philippe Mathieu-Daudé wrote: > Date: Fri, 20 Oct 2023 13:30:50 +0200 > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Subject: Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target > agnostic > > Hi Zhao, > > On 20/10/23 07:50, Zhao Liu wrote: > > Hi Philippe, > > > > On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote: > > > Date: Fri, 13 Oct 2023 16:00:59 +0200 > > > From: Philippe Mathieu-Daudé <philmd@linaro.org> > > > Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic > > > X-Mailer: git-send-email 2.41.0 > > > > > > Since v1: > > > - Added R-b tags > > > - Addressed Richard comments > > > - Postponed OBJECT_DECLARE_CPU_TYPE() changes > > > > > > A heterogeneous machine must be able to instantiate CPUs > > > from different architectures. > > > > Does this mean the different ISA cores in heterogeneous machine? > > Yes. Currently the ARM target already allows you to do that > (multiple ISA cores within the same architecture), see the > xlnx-zcu102 and fby35 machines. Okay, I'll have a look at it. > > > And is this case for TCG? > > This is *only* for TCG. I expect hardware accel + TCG to be > theoretically possible, but no interest has been shown for > it. Anyhow this requires heterogeneous TCG as a first step. Thanks, got it. > > > > In order to do that, the > > > common hw/ code has to access to the QOM CPU definitions > > > from various architecture. > > > > About this kind of heterogeneous machine with multiple CPUs, is there > > any initial configuration command line example? > > I'm prototyping in plain C but our plan is to start with a > QMP prototype. Command line configuration is not an option, > we decided to ignore it. I'll describe that better in a RFC > document I should post soon. Looking forward to your RFC! For accel, I am currently working in this direction (to convert all CPU topology levels to devices and to create heterogeneous topology via "-device") as the following: -device cpu-socket,id=sock0 \ -device cpu-die,id=die0,parent=sock0 \ -device cpu-die,id=die1,parent=sock0 \ -device cpu-cluster,id=cluster0,parent=die0 \ -device cpu-cluster,id=cluster1,parent=die0 \ -device x86-intel-core,id=core0,parent=cluster0,threads=3 \ -device x86-intel-atom,id=core1,parent=cluster1,threads=2 \ -device x86-intel-core,id=core2,parent=cluster0,threads=3 At present, I have a prototype and am sorting out the RFC. From your description, I understand that we have no conflict. Also welcome your thoughts and hope that I can go in the same direction with you. ;-) Regards, Zhao