Message ID | IA1PR20MB49531C1C34C3E972DBBA4151BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com |
---|---|
Headers | show |
Series | Add Huashan Pi board support | expand |
On 2023/10/9 19:26, Inochi Amaoto wrote: > Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > new file mode 100644 > index 000000000000..3864d34b0100 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> This include is not required. > +#include "cv180x.dtsi" > + > +/ { > + compatible = "sophgo,cv1812h"; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x10000000>; > + }; What's this defined for , I see this is different against cv1800b. > + > + soc { > + interrupt-parent = <&plic>; > + > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + }; > + > + clint: timer@74000000 { > + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > + reg = <0x74000000 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > + }; > + }; > +}; > -- > 2.42.0 >
>On 2023/10/9 19:26, Inochi Amaoto wrote: >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> --- >> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi >> new file mode 100644 >> index 000000000000..3864d34b0100 >> --- /dev/null >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi >> @@ -0,0 +1,36 @@ >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >> +/* >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> >> + */ >> + >> +#include <dt-bindings/interrupt-controller/irq.h> >This include is not required. Thx. >> +#include "cv180x.dtsi" >> + >> +/ { >> + compatible = "sophgo,cv1812h"; >> + >> + memory@80000000 { >> + device_type = "memory"; >> + reg = <0x80000000 0x10000000>; >> + }; >What's this defined for , I see this is different against cv1800b. CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the size is different. I write this node here because the RAM is embedded and fixed size, and leave it in the board DT is unnecessary. >> + >> + soc { >> + interrupt-parent = <&plic>; >> + >> + plic: interrupt-controller@70000000 { >> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; >> + reg = <0x70000000 0x4000000>; >> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; >> + interrupt-controller; >> + #address-cells = <0>; >> + #interrupt-cells = <2>; >> + riscv,ndev = <101>; >> + }; >> + >> + clint: timer@74000000 { >> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; >> + reg = <0x74000000 0x10000>; >> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; >> + }; >> + }; >> +}; >> -- >> 2.42.0 >> >
On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote: > >On 2023/10/9 19:26, Inochi Amaoto wrote: > >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. > >> > >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > >> --- > >> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++ > >> 1 file changed, 36 insertions(+) > >> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > >> > >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > >> new file mode 100644 > >> index 000000000000..3864d34b0100 > >> --- /dev/null > >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > >> @@ -0,0 +1,36 @@ > >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > >> +/* > >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > >> + */ > >> + > >> +#include <dt-bindings/interrupt-controller/irq.h> > >This include is not required. > > Thx. I can drop this include on application. Is the rest of the series okay with you Chen Wang? Thanks, Conor. > > >> +#include "cv180x.dtsi" > >> + > >> +/ { > >> + compatible = "sophgo,cv1812h"; > >> + > >> + memory@80000000 { > >> + device_type = "memory"; > >> + reg = <0x80000000 0x10000000>; > >> + }; > >What's this defined for , I see this is different against cv1800b. > > CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the > size is different. I write this node here because the RAM is embedded > and fixed size, and leave it in the board DT is unnecessary. > > >> + > >> + soc { > >> + interrupt-parent = <&plic>; > >> + > >> + plic: interrupt-controller@70000000 { > >> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; > >> + reg = <0x70000000 0x4000000>; > >> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > >> + interrupt-controller; > >> + #address-cells = <0>; > >> + #interrupt-cells = <2>; > >> + riscv,ndev = <101>; > >> + }; > >> + > >> + clint: timer@74000000 { > >> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > >> + reg = <0x74000000 0x10000>; > >> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > >> + }; > >> + }; > >> +}; > >> -- > >> 2.42.0 > >> > >
On Mon, Oct 09, 2023 at 07:25:14PM +0800, Inochi Amaoto wrote: > Huashan Pi board is an embedded development platform based on the > CV1812H chip. Add minimal device tree files for this board. > Currently, it can boot to a basic shell. > > NOTE: this series is based on the Jisheng's Milk-V Duo patch. > > Link: https://en.sophgo.com/product/introduce/huashan.html > Link: https://en.sophgo.com/product/introduce/cv181xH.html > > Changed from v1: > 1. split the patch into several patch and refactor them. > > Inochi Amaoto (7): > dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic > dt-bindings: timer: Add SOPHGO CV1812H clint > dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles > riscv: dts: sophgo: Separate common devices from cv1800b soc > riscv: dts: sophgo: cv180x: Add gpio devices > riscv: dts: sophgo: add initial CV1812H SoC device tree > riscv: dts: sophgo: add Huashan Pi board device tree For the patch series: Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > > .../sifive,plic-1.0.0.yaml | 1 + > .../devicetree/bindings/riscv/sophgo.yaml | 4 + > .../bindings/timer/sifive,clint.yaml | 1 + > arch/riscv/boot/dts/sophgo/Makefile | 1 + > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 91 ++++++++++++++---- > .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 ++++++++++ > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++ > 8 files changed, 165 insertions(+), 112 deletions(-) > copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (58%) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > -- > 2.42.0 >
On 09/10/2023 13:25, Inochi Amaoto wrote: > Huashan Pi board is an embedded development platform based on the > CV1812H chip. Add minimal device tree files for this board. > Currently, it can boot to a basic shell. > > NOTE: this series is based on the Jisheng's Milk-V Duo patch. Which is? This must be clear dependency - lore link. Best regards, Krzysztof