| Message ID | 20231010092901.99189-11-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target: Make 'cpu-qom.h' really target agnostic | expand |
On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote: > TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 > definitions which are target specific. Such target specific > definition taints "cpu-qom.h". > > Since "cpu-qom.h" must be target agnostic, remove its target > specific definition uses by inlining TYPE_RISCV_CPU_BASE in the > two machines using it. > > "target/riscv/cpu-qom.h" is now fully target agnostic. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/riscv/cpu-qom.h | 8 +------- > hw/riscv/spike.c | 8 +++++++- > hw/riscv/virt.c | 8 +++++++- > 3 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 8cb67b84a4..f607687384 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -1,5 +1,5 @@ > /* > - * QEMU RISC-V CPU QOM header > + * QEMU RISC-V CPU QOM header (target agnostic) > * > * Copyright (c) 2023 Ventana Micro Systems Inc. > * > @@ -43,12 +43,6 @@ > #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > -#if defined(TARGET_RISCV32) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 > -#elif defined(TARGET_RISCV64) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 > -#endif > - > typedef struct CPUArchState CPURISCVState; > > OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 81f7e53aed..eae49da6d6 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data) > mc->init = spike_board_init; > mc->max_cpus = SPIKE_CPUS_MAX; > mc->is_default = true; > - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; > +#if defined(TARGET_RISCV32) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; > +#elif defined(TARGET_RISCV64) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; > +#else > +#error unsupported target > +#endif > mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; > mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 5edc1d98d2..620a4e5f07 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) > mc->desc = "RISC-V VirtIO board"; > mc->init = virt_machine_init; > mc->max_cpus = VIRT_CPUS_MAX; > - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; > +#if defined(TARGET_RISCV32) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; > +#elif defined(TARGET_RISCV64) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; > +#else > +#error unsupported target > +#endif Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > mc->pci_allow_0_address = true; > mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
On Tue, Oct 10, 2023 at 7:32 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 > definitions which are target specific. Such target specific > definition taints "cpu-qom.h". > > Since "cpu-qom.h" must be target agnostic, remove its target > specific definition uses by inlining TYPE_RISCV_CPU_BASE in the > two machines using it. > > "target/riscv/cpu-qom.h" is now fully target agnostic. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu-qom.h | 8 +------- > hw/riscv/spike.c | 8 +++++++- > hw/riscv/virt.c | 8 +++++++- > 3 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 8cb67b84a4..f607687384 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -1,5 +1,5 @@ > /* > - * QEMU RISC-V CPU QOM header > + * QEMU RISC-V CPU QOM header (target agnostic) > * > * Copyright (c) 2023 Ventana Micro Systems Inc. > * > @@ -43,12 +43,6 @@ > #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > -#if defined(TARGET_RISCV32) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 > -#elif defined(TARGET_RISCV64) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 > -#endif > - > typedef struct CPUArchState CPURISCVState; > > OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 81f7e53aed..eae49da6d6 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data) > mc->init = spike_board_init; > mc->max_cpus = SPIKE_CPUS_MAX; > mc->is_default = true; > - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; > +#if defined(TARGET_RISCV32) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; > +#elif defined(TARGET_RISCV64) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; > +#else > +#error unsupported target > +#endif > mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; > mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 5edc1d98d2..620a4e5f07 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) > mc->desc = "RISC-V VirtIO board"; > mc->init = virt_machine_init; > mc->max_cpus = VIRT_CPUS_MAX; > - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; > +#if defined(TARGET_RISCV32) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; > +#elif defined(TARGET_RISCV64) > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; > +#else > +#error unsupported target > +#endif > mc->pci_allow_0_address = true; > mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; > -- > 2.41.0 > >
On 10/10/23 02:28, Philippe Mathieu-Daudé wrote: > TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 > definitions which are target specific. Such target specific > definition taints "cpu-qom.h". > > Since "cpu-qom.h" must be target agnostic, remove its target > specific definition uses by inlining TYPE_RISCV_CPU_BASE in the > two machines using it. > > "target/riscv/cpu-qom.h" is now fully target agnostic. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/riscv/cpu-qom.h | 8 +------- > hw/riscv/spike.c | 8 +++++++- > hw/riscv/virt.c | 8 +++++++- > 3 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 8cb67b84a4..f607687384 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -1,5 +1,5 @@ > /* > - * QEMU RISC-V CPU QOM header > + * QEMU RISC-V CPU QOM header (target agnostic) > * > * Copyright (c) 2023 Ventana Micro Systems Inc. > * > @@ -43,12 +43,6 @@ > #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > -#if defined(TARGET_RISCV32) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 > -#elif defined(TARGET_RISCV64) > -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 > -#endif Move to cpu.h (or elsewhere) instead of replicating in two hw/ files? r~
On 13/10/23 06:13, Richard Henderson wrote: > On 10/10/23 02:28, Philippe Mathieu-Daudé wrote: >> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 >> definitions which are target specific. Such target specific >> definition taints "cpu-qom.h". >> >> Since "cpu-qom.h" must be target agnostic, remove its target >> specific definition uses by inlining TYPE_RISCV_CPU_BASE in the >> two machines using it. >> >> "target/riscv/cpu-qom.h" is now fully target agnostic. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> target/riscv/cpu-qom.h | 8 +------- >> hw/riscv/spike.c | 8 +++++++- >> hw/riscv/virt.c | 8 +++++++- >> 3 files changed, 15 insertions(+), 9 deletions(-) >> @@ -43,12 +43,6 @@ >> #define TYPE_RISCV_CPU_VEYRON_V1 >> RISCV_CPU_TYPE_NAME("veyron-v1") >> #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") >> -#if defined(TARGET_RISCV32) >> -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 >> -#elif defined(TARGET_RISCV64) >> -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 >> -#endif > > Move to cpu.h (or elsewhere) instead of replicating in two hw/ files? Yes, better.
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 8cb67b84a4..f607687384 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU RISC-V CPU QOM header + * QEMU RISC-V CPU QOM header (target agnostic) * * Copyright (c) 2023 Ventana Micro Systems Inc. * @@ -43,12 +43,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - typedef struct CPUArchState CPURISCVState; OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 81f7e53aed..eae49da6d6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data) mc->init = spike_board_init; mc->max_cpus = SPIKE_CPUS_MAX; mc->is_default = true; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; +#if defined(TARGET_RISCV32) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; +#elif defined(TARGET_RISCV64) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; +#else +#error unsupported target +#endif mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5edc1d98d2..620a4e5f07 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->desc = "RISC-V VirtIO board"; mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; +#if defined(TARGET_RISCV32) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; +#elif defined(TARGET_RISCV64) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; +#else +#error unsupported target +#endif mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by inlining TYPE_RISCV_CPU_BASE in the two machines using it. "target/riscv/cpu-qom.h" is now fully target agnostic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/riscv/cpu-qom.h | 8 +------- hw/riscv/spike.c | 8 +++++++- hw/riscv/virt.c | 8 +++++++- 3 files changed, 15 insertions(+), 9 deletions(-)