| Message ID | 20231005155618.700312-11-peter.griffin@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 05/10/2023 17:56, Peter Griffin wrote: > CMU_APM generates clocks for the Active Power Management > controller. Add clock indices for those muxs, dividers and > gates. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) Please squash it with previous patch. Best regards, Krzysztof
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h index d1e216a33aeb..d9b8299fcc0b 100644 --- a/include/dt-bindings/clock/gs101.h +++ b/include/dt-bindings/clock/gs101.h @@ -201,4 +201,21 @@ #define CLK_GOUT_BO_BUS 184 #define CLK_GOUT_CMU_BOOST 185 +/* CMU_APM */ + +#define CLK_MOUT_APM_FUNC 1 +#define CLK_MOUT_APM_FUNCSRC 2 +#define CLK_DOUT_APM_BOOST 3 +#define CLK_DOUT_APM_USI0_UART 4 +#define CLK_DOUT_APM_USI0_USI 5 +#define CLK_DOUT_APM_USI1_UART 6 +#define CLK_GOUT_APM_FUNC 7 +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 8 +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 9 +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 10 +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 11 +#define CLK_APM_PLL_DIV2_APM 12 +#define CLK_APM_PLL_DIV4_APM 13 +#define CLK_APM_PLL_DIV16_APM 14 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
CMU_APM generates clocks for the Active Power Management controller. Add clock indices for those muxs, dividers and gates. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)