| Message ID | 20231005155618.700312-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 05/10/2023 17:55, Peter Griffin wrote: > Add the gs101 SoC interrupt header that provides human readable > constants for all the IRQs in the SoC. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++ > 1 file changed, 758 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/gs101.h > > diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h > new file mode 100644 > index 000000000000..51c8eb54eca2 > --- /dev/null > +++ b/include/dt-bindings/interrupt-controller/gs101.h > @@ -0,0 +1,758 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * This header provides constants for gs101 interrupt controller. > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H > + > +#define ITNO IRQ_TYPE_NONE > +#define ITER IRQ_TYPE_EDGE_RISING > +#define ITEF IRQ_TYPE_EDGE_FALLING > +#define ITEB IRQ_TYPE_EDGE_BOTH > +#define ITLH IRQ_TYPE_LEVEL_HIGH > +#define ITLL IRQ_TYPE_LEVEL_LOW No, these are not bindings. > + > +#define IRQ_ALIVE_EINT0 0 > +#define IRQ_ALIVE_EINT1 1 We do not keep interrupt numbers as bindings. Please drop entire file. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > GS101 has three different SYSREG controllers, add dedicated > compatibles for them to the documentation. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > index 163e912e9cad..02f580d6489b 100644 > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > @@ -50,6 +50,13 @@ properties: > - samsung,exynosautov9-peric1-sysreg > - const: samsung,exynosautov9-sysreg > - const: syscon > + - items: > + - enum: > + - google,gs101-peric0-sysreg > + - google,gs101-peric1-sysreg > + - google,gs101-apm-sysreg > + - const: google,gs101-sysreg Please drop this one compatible. Exynos has it only for backwards compatibility. Also, please put entire list ("items") before such entry for samsung,exynos5433-sysreg, so everything is more-or-less ordered alphabetically, by the fallback compatible. > + - const: syscon > > reg: > maxItems: 1 Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the > dt-schema documentation. > > gs101 SoC has two CPU clusters and each cluster has its own dedicated > watchdog timer (similar to exynos850 and exynosautov9 SoCs). > > These WDT instances are controlled using different bits in PMU > registers. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > index 8fb6656ba0c2..30f5949037fc 100644 > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > @@ -24,6 +24,8 @@ properties: > - samsung,exynos7-wdt # for Exynos7 > - samsung,exynos850-wdt # for Exynos850 > - samsung,exynosautov9-wdt # for Exynosautov9 > + - google,gs101-wdt # for Google gs101 > + - google,gs201-wdt # for Google gs101 Alphanumerical order. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > CMU_TOP geneerates clocks for all the other CMU units. Add clock > indices for those PLLs, muxes, dividers and gates. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++ > 1 file changed, 204 insertions(+) > create mode 100644 include/dt-bindings/clock/gs101.h This patch should be squashed with bindings for this clock. Header on its own makes little sense. Also, filename should match compatible (vendor prefix, Soc-clock etc). > > diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h > new file mode 100644 > index 000000000000..d1e216a33aeb > --- /dev/null > +++ b/include/dt-bindings/clock/gs101.h > @@ -0,0 +1,204 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > CMU_APM generates clocks for the Active Power Management > controller. Add clock indices for those muxs, dividers and > gates. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) Please squash it with previous patch. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. It features: > * 4xA55 little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > > This commit adds the basic device tree for gs101 (SoC) and oriole > (pixel 6). Further platform support will be added over time. > > It has been tested with a minimal busybox initramfs and boots to > a shell. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > arch/arm64/Kconfig.platforms | 6 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/google/Makefile | 6 + > arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ > arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + > arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ Please split adding DTSI from adding DTS into two patches. > 7 files changed, 1733 insertions(+) > create mode 100644 arch/arm64/boot/dts/google/Makefile > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 6069120199bb..a5ed1b719488 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -107,6 +107,12 @@ config ARCH_EXYNOS > help > This enables support for ARMv8 based Samsung Exynos SoC family. > > +config ARCH_GOOGLE_TENSOR > + bool "Google Tensor SoC fmaily" > + depends on ARCH_EXYNOS > + help > + Support for ARMv8 based Google Tensor platforms. > + > config ARCH_SPARX5 > bool "Microchip Sparx5 SoC family" > select PINCTRL > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 30dd6347a929..a4ee7b628114 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -13,6 +13,7 @@ subdir-y += broadcom > subdir-y += cavium > subdir-y += exynos > subdir-y += freescale > +subdir-y += google > subdir-y += hisilicon > subdir-y += intel > subdir-y += lg > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile > new file mode 100644 > index 000000000000..6d2026a767d4 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/Makefile > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \ > + gs101-oriole.dtb \ > + > + Too many blank lines > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts > new file mode 100644 > index 000000000000..e531a39a76a4 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts > @@ -0,0 +1,68 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Oriole DVT Device Tree > + * > + * Copyright 2021-2023 Google,LLC > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include "gs101-pinctrl.h" > +#include "gs101.dtsi" > + > +/ { > + model = "Oriole DVT"; > + compatible = "google,gs101-oriole", "google,gs101"; > +}; > + > +&pinctrl_1 { > + key_voldown: key-voldown-pins { > + samsung,pins = "gpa7-3"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + key_volup: key-volup-pins { > + samsung,pins = "gpa8-1"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_0 { > + key_power: key-power-pins { > + samsung,pins = "gpa10-1"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&gpio_keys { SoC does not have gpio-keys. That's entirely a property of the board. > + status = "okay"; Drop > + pinctrl-names = "default"; > + pinctrl-0 = <&key_voldown &key_volup &key_power>; Blank line > + button-vol-down { > + label = "KEY_VOLUMEDOWN"; > + linux,code = <114>; > + gpios = <&gpa7 3 0xf>; > + wakeup-source; > + }; Blank line > + button-vol-up { > + label = "KEY_VOLUMEUP"; > + linux,code = <115>; > + gpios = <&gpa8 1 0xf>; > + wakeup-source; > + }; Blank line > + button-power { > + label = "KEY_POWER"; > + linux,code = <116>; > + gpios = <&gpa10 1 0xf>; > + wakeup-source; > + }; > +}; > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > new file mode 100644 > index 000000000000..24825205ede8 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > @@ -0,0 +1,1134 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC pin-mux and pin-config device tree source > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#include <dt-bindings/interrupt-controller/gs101.h> > +#include <arm64/exynos/exynos-pinctrl.h> > +#include "gs101-pinctrl.h" > + > +/ { > + /* GPIO_ALIVE */ > + pinctrl@174d0000 { > + gpa0: gpa0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>; > + }; Blank line > + gpa1: gpa1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>; > + }; > + gpa2: gpa2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>; > + }; > + gpa3: gpa3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>; > + }; > + gpa4: gpa4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>; > + }; > + gpa5: gpa5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>; > + }; > + gpa9: gpa9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>; > + }; > + gpa10: gpa10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>; > + }; > + > + uart15_bus: uart15-bus-pins { > + samsung,pins = "gpa2-3", "gpa2-4"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + > + uart16_bus: uart16-bus-pins { > + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; You should rather create macros for your SoC... unless you are 100% sure this matches Exynos arm64 pinctrl. ... > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..acc77c684f0d > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright (c) 2020-2023 Google, LLC. > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi > new file mode 100644 > index 000000000000..0bd43745f6fa > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101.dtsi > @@ -0,0 +1,501 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#include <dt-bindings/clock/gs101.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/gs101.h> > + > +#include "gs101-pinctrl.dtsi" > + > +/ { > + compatible = "google,gs101"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <1>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + pinctrl3 = &pinctrl_3; > + pinctrl4 = &pinctrl_4; > + pinctrl5 = &pinctrl_5; > + pinctrl6 = &pinctrl_6; > + pinctrl7 = &pinctrl_7; > + Stray blank line > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; Blank line > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; Blank line > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0000>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; Blank line > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0100>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0200>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0300>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0400>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + cpu5: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0500>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + cpu6: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0600>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + cpu7: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0700>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + ANANKE_CPU_SLEEP: cpu-ananke-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <70>; > + exit-latency-us = <160>; > + min-residency-us = <2000>; > + status = "okay"; Drop status. Okay is by default. > + }; > + > + ENYO_CPU_SLEEP: cpu-enyo-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <150>; > + exit-latency-us = <190>; > + min-residency-us = <2500>; > + status = "okay"; Drop status. Okay is by default. > + }; > + > + HERA_CPU_SLEEP: cpu-hera-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <235>; > + exit-latency-us = <220>; > + min-residency-us = <3500>; > + status = "okay"; Drop status. Okay is by default. > + }; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + tpu_fw_reserved: tpu_fw@93000000 { No underscores in node names. Use hyphens. > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss_log_reserved@fd3f0000 { > + reg = <0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 { > + reg = <0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr_log_reserved@fd800000 { > + reg = <0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 { > + reg = <0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + /* bootloader requires ect node */ > + ect { > + parameter_address = <0x90000000>; > + parameter_size = <0x53000>; > + }; > + > + chosen { Please order the nodes by name. > + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused"; None of these bootargs are suitable for wide, mainline use. Please drop. > + }; > + > + gic: interrupt-controller@10400000 { This cannot be outside of SoC. > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x0 0x10400000 0x10000>, /* GICD */ > + <0x0 0x10440000 0x100000>; /* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <24576000>; > + }; > + > + ext_24_5m: ext_24_5m { clock-1 > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24576000>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: ext_200m { clock-2 > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + clock-output-names = "ext-200m"; > + }; > + > + /* GPIO_ALIVE */ > + pinctrl_0: pinctrl@174d0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x174d0000 0x00001000>; 0x0 Please open Tesla FSD or Exynos850 for examples. Also, this cannot be outside of SoC. There is no way this passes dtbs_check W=1. Nodes in MMIO-bus should be ordered by unit address. > + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint"; > + }; > + }; > + > + /* GPIO_FAR_ALIVE */ > + pinctrl_1: pinctrl@174e0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x174e0000 0x00001000>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint"; > + }; > + }; > + > + /* GPIO_GSACORE */ > + pinctrl_2: pinctrl@17a80000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x17a80000 0x00001000>; > + }; > + /* GPIO_GSACTRL */ > + pinctrl_3: pinctrl@17940000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x17940000 0x00001000>; > + }; > + /* GPIO_PERIC0 */ > + pinctrl_4: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x10840000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_PERIC1 */ > + pinctrl_5: pinctrl@10c40000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x10C40000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_HSI1 */ > + pinctrl_6: pinctrl@11840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x11840000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_HSI2 */ > + pinctrl_7: pinctrl@14440000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x14440000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + arm-pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + sysreg_apm: syscon@174204e0 { > + compatible = "google,gs101-apm-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x174204e0 0x1000>; > + }; > + > + sysreg_peric0: syscon@10821000 { > + compatible = "google,gs101-peric0-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x10821000 0x40000>; > + }; > + > + sysreg_peric1: syscon@10c21000 { > + compatible = "google,gs101-peric1-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x10C21000 0x40000>; > + }; > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; One space before = > + clock-output-names = "pclk"; > + }; > + > + serial_0: serial@10a00000 { > + compatible = "samsung,exynos850-uart"; You need also specific compatible for GS. Fallback can stay. > + reg = <0x0 0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; > + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clock-names = "uart", "clk_uart_baud0"; > + status = "okay"; Drop, it's default. > + }; > + > + pmu_system_controller: system-controller@17460000 { > + compatible = "google,gs101-pmu", "syscon"; > + reg = <0x0 0x17460000 0x10000>; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x0 0x10060000 0x100>; > + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + timeout-sec = <30>; This is rather property of the board. > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + }; > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x0 0x10070000 0x100>; > + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + timeout-sec = <30>; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + cmu_top: clock-controller@1e080000 { > + compatible = "google,gs101-cmu-top"; > + reg = <0x0 0x1e080000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + > + cmu_apm: clock-controller@17400000 { > + compatible = "google,gs101-cmu-apm"; > + reg = <0x0 0x17400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x0 0x10010000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; > + clock-names = "oscclk", "dout_cmu_misc_bus"; > + }; > + > + dsu-pmu-0 { > + compatible = "arm,dsu-pmu"; > + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; > + > + gpio_keys: gpio_keys { > + compatible = "gpio-keys"; That's not a property of the SoC. > + }; > + Stray blank line. > +}; Best regards, Krzysztof
On 05/10/2023 17:55, Peter Griffin wrote: > Hi folks, > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > Currently DT is just added for the gs101 SoC and Oriole. Thanks for submitting the patches. Nice work! This is basically a custom-made variant of Exynos made by Samsung for Google. Something similar what is with Tesla FSD (and Axis Artpec-8 which was not upstreamed, AFAIR). Many, many drivers and bindings will be re-used. I want to be sure that GS101 fits into existing Samsung Exynos support, re-uses it as much as possible and extend when necessary without breaking anything. Therefore, when the patches are ready, I would like to be the one applying entire set and future submissions through Samsung SoC tree, just like I am doing it with Tesla FSD, so I keep entire Samsung-ecosystem in shape. This also means that you are lucky to be selected to: https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst joining there Tesla FSD and entire Samsung Exynos family :) I hope that's ok. Best regards, Krzysztof
On 10/05/2023, Peter Griffin wrote: > Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the > dt-schema documentation. > > gs101 SoC has two CPU clusters and each cluster has its own dedicated > watchdog timer (similar to exynos850 and exynosautov9 SoCs). > > These WDT instances are controlled using different bits in PMU > registers. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > index 8fb6656ba0c2..30f5949037fc 100644 > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > @@ -24,6 +24,8 @@ properties: > - samsung,exynos7-wdt # for Exynos7 > - samsung,exynos850-wdt # for Exynos850 > - samsung,exynosautov9-wdt # for Exynosautov9 > + - google,gs101-wdt # for Google gs101 > + - google,gs201-wdt # for Google gs101 For "google,gs201-wdt the comment should be "for Google gs201". Regards, Will > > reg: > maxItems: 1 > @@ -42,13 +44,13 @@ properties: > samsung,cluster-index: > $ref: /schemas/types.yaml#/definitions/uint32 > description: > - Index of CPU cluster on which watchdog is running (in case of Exynos850) > + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01) > > samsung,syscon-phandle: > $ref: /schemas/types.yaml#/definitions/phandle > description: > Phandle to the PMU system controller node (in case of Exynos5250, > - Exynos5420, Exynos7 and Exynos850). > + Exynos5420, Exynos7, Exynos850 and gsx01). > > required: > - compatible > @@ -69,6 +71,8 @@ allOf: > - samsung,exynos7-wdt > - samsung,exynos850-wdt > - samsung,exynosautov9-wdt > + - google,gs101-wdt > + - google,gs201-wdt > then: > required: > - samsung,syscon-phandle > @@ -79,6 +83,8 @@ allOf: > enum: > - samsung,exynos850-wdt > - samsung,exynosautov9-wdt > + - google,gs101-wdt > + - google,gs201-wdt > then: > properties: > clocks: > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6. nit: Thesee -> These > > pll0516x: Integrer PLL with high frequency > pll0517x: Integrer PLL with middle frequency > pll0518x: Integrer PLL with low frequency nit: Integrer -> Integer? Regards, Will > > PLL0516x > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) > > PLL0517x and PLL0518x > FOUT = (MDIV * FIN)/PDIV*2^SDIV) > > The PLLs are similar enough to pll_0822x that the same code can handle > both. The main difference is the change in the fout formula for the > high frequency 0516 pll. > > Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. > MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. > > When defining the PLL the "con" parameter should be set to CON3 > register, like this > > PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > NULL), > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/clk-pll.c | 9 ++++++++- > drivers/clk/samsung/clk-pll.h | 3 +++ > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 74934c6182ce..4ef9fea2a425 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, > pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; > sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; > > - fvco *= mdiv; > + if (pll->type == pll_0516x) > + fvco = fvco * 2 * mdiv; > + else > + fvco *= mdiv; > + > do_div(fvco, (pdiv << sdiv)); > > return (unsigned long)fvco; > @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, > case pll_1417x: > case pll_0818x: > case pll_0822x: > + case pll_0516x: > + case pll_0517x: > + case pll_0518x: > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; > if (!pll->rate_table) > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h > index 0725d485c6ee..ffd3d52c0dec 100644 > --- a/drivers/clk/samsung/clk-pll.h > +++ b/drivers/clk/samsung/clk-pll.h > @@ -38,6 +38,9 @@ enum samsung_pll_type { > pll_0822x, > pll_0831x, > pll_142xx, > + pll_0516x, > + pll_0517x, > + pll_0518x, > }; > > #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > This patch adds all the registers for the APM clock controller unit. > > We register all the muxes and dividers, but only a few of the > gates currently for PMU and GPIO. > > One clock is marked CLK_IS_CRITICAL because the system > hangs is this clock is disabled. nit: hangs if this clock... Regards, Will > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++ > 1 file changed, 300 insertions(+) > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > index 4c58fcc899be..b98b42f54949 100644 > --- a/drivers/clk/samsung/clk-gs101.c > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -19,6 +19,7 @@ > > /* NOTE: Must be equal to the last clock ID increased by one */ > #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1) > +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1) > > /* ---- CMU_TOP ------------------------------------------------------------- */ > > @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np) > /* Register CMU_TOP early, as it's a dependency for other early domains */ > CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > gs101_cmu_top_init); > + > +/* ---- CMU_APM ------------------------------------------------------------- */ > +/* Register Offset definitions for CMU_APM (0x17400000) */ > +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 > +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 > +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c > +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 > +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 > +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c > +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc > +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 > +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 > +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 > +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c > +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 > +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 > +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 > +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c > +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 > +#define QCH_CON_APBIF_RTC_QCH 0x3024 > +#define QCH_CON_APBIF_TRTC_QCH 0x3028 > +#define QCH_CON_APM_CMU_APM_QCH 0x302c > +#define QCH_CON_APM_USI0_UART_QCH 0x3030 > +#define QCH_CON_APM_USI0_USI_QCH 0x3034 > +#define QCH_CON_APM_USI1_UART_QCH 0x3038 > +#define QCH_CON_D_TZPC_APM_QCH 0x303c > +#define QCH_CON_GPC_APM_QCH 0x3040 > +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 > +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 > +#define QCH_CON_INTMEM_QCH 0x304c > +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 > +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 > +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 > +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c > +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 > +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 > +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 > +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c > +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 > +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 > +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c > +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 > +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 > +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 > +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 > +#define QCH_CON_SPEEDY_APM_QCH 0x3098 > +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c > +#define QCH_CON_SSMT_D_APM_QCH 0x30a0 > +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 > +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 > +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac > +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 > +#define QCH_CON_SYSREG_APM_QCH 0x30b8 > +#define QCH_CON_UASC_APM_QCH 0x30bc > +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 > +#define QCH_CON_UASC_G_SWD_QCH 0x30c4 > +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 > +#define QCH_CON_UASC_P_APM_QCH 0x30cc > +#define QCH_CON_WDT_APM_QCH 0x30d0 > +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 > + > +static const unsigned long apm_clk_regs[] __initconst = { > + APM_CMU_APM_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, > + CLK_CON_DIV_DIV_CLK_APM_BOOST, > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, > + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, > +}; > + > +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" }; > +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" }; > + > +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { > + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000), > + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000), > + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000), > +}; > + > +static const struct samsung_mux_clock apm_mux_clks[] __initconst = { > + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), > + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), > +}; > + > +static const struct samsung_div_clock apm_div_clks[] __initconst = { > + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), > + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), > + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), > + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), > +}; > + > +static const struct samsung_gate_clock apm_gate_clks[] __initconst = { > + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + 21, CLK_IS_CRITICAL, 0), > + > + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info apm_cmu_info __initconst = { > + .mux_clks = apm_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), > + .div_clks = apm_div_clks, > + .nr_div_clks = ARRAY_SIZE(apm_div_clks), > + .gate_clks = apm_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), > + .fixed_clks = apm_fixed_clks, > + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), > + .nr_clk_ids = APM_NR_CLK, > + .clk_regs = apm_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), > +}; > + > +/* ---- platform_driver ----------------------------------------------------- */ > + > +static int __init gs101_cmu_probe(struct platform_device *pdev) > +{ > + const struct samsung_cmu_info *info; > + struct device *dev = &pdev->dev; > + > + info = of_device_get_match_data(dev); > + exynos_arm64_register_cmu(dev, dev->of_node, info); > + > + return 0; > +} > + > +static const struct of_device_id gs101_cmu_of_match[] = { > + { > + .compatible = "google,gs101-cmu-apm", > + .data = &apm_cmu_info, > + }, > +}; > + > +static struct platform_driver gs101_cmu_driver __refdata = { > + .driver = { > + .name = "gs101-cmu", > + .of_match_table = gs101_cmu_of_match, > + .suppress_bind_attrs = true, > + }, > + .probe = gs101_cmu_probe, > +}; > + > +static int __init gs101_cmu_init(void) > +{ > + return platform_driver_register(&gs101_cmu_driver); > +} > +core_initcall(gs101_cmu_init); > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > This patch adds all the registers for the APM clock controller unit. > > We register all the muxes and dividers, but only a few of the > gates currently for PMU and GPIO. > > One clock is marked CLK_IS_CRITICAL because the system > hangs is this clock is disabled. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++ > 1 file changed, 300 insertions(+) > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > index 4c58fcc899be..b98b42f54949 100644 > --- a/drivers/clk/samsung/clk-gs101.c > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -19,6 +19,7 @@ > > /* NOTE: Must be equal to the last clock ID increased by one */ > #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1) > +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1) > > /* ---- CMU_TOP ------------------------------------------------------------- */ > > @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np) > /* Register CMU_TOP early, as it's a dependency for other early domains */ > CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > gs101_cmu_top_init); > + > +/* ---- CMU_APM ------------------------------------------------------------- */ > +/* Register Offset definitions for CMU_APM (0x17400000) */ > +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 > +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 > +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c > +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 > +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 > +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c > +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc > +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 > +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 > +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 > +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c > +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 > +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 > +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 > +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c > +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 > +#define QCH_CON_APBIF_RTC_QCH 0x3024 > +#define QCH_CON_APBIF_TRTC_QCH 0x3028 > +#define QCH_CON_APM_CMU_APM_QCH 0x302c > +#define QCH_CON_APM_USI0_UART_QCH 0x3030 > +#define QCH_CON_APM_USI0_USI_QCH 0x3034 > +#define QCH_CON_APM_USI1_UART_QCH 0x3038 > +#define QCH_CON_D_TZPC_APM_QCH 0x303c > +#define QCH_CON_GPC_APM_QCH 0x3040 > +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 > +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 > +#define QCH_CON_INTMEM_QCH 0x304c > +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 > +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 > +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 > +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c > +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 > +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 > +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 > +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c > +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 > +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 > +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c > +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 > +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 > +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 > +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 > +#define QCH_CON_SPEEDY_APM_QCH 0x3098 > +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c > +#define QCH_CON_SSMT_D_APM_QCH 0x30a0 > +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 > +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 > +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac > +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 > +#define QCH_CON_SYSREG_APM_QCH 0x30b8 > +#define QCH_CON_UASC_APM_QCH 0x30bc > +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 > +#define QCH_CON_UASC_G_SWD_QCH 0x30c4 > +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 > +#define QCH_CON_UASC_P_APM_QCH 0x30cc > +#define QCH_CON_WDT_APM_QCH 0x30d0 > +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 > + > +static const unsigned long apm_clk_regs[] __initconst = { > + APM_CMU_APM_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, > + CLK_CON_DIV_DIV_CLK_APM_BOOST, > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, > + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, > +}; > + > +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" }; > +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" }; > + > +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { > + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000), > + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000), > + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000), > +}; > + > +static const struct samsung_mux_clock apm_mux_clks[] __initconst = { > + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), > + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), > +}; > + > +static const struct samsung_div_clock apm_div_clks[] __initconst = { > + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), > + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), > + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), > + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), > +}; > + > +static const struct samsung_gate_clock apm_gate_clks[] __initconst = { > + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + 21, CLK_IS_CRITICAL, 0), > + > + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info apm_cmu_info __initconst = { > + .mux_clks = apm_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), > + .div_clks = apm_div_clks, > + .nr_div_clks = ARRAY_SIZE(apm_div_clks), > + .gate_clks = apm_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), > + .fixed_clks = apm_fixed_clks, > + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), > + .nr_clk_ids = APM_NR_CLK, > + .clk_regs = apm_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), > +}; > + > +/* ---- platform_driver ----------------------------------------------------- */ > + > +static int __init gs101_cmu_probe(struct platform_device *pdev) > +{ > + const struct samsung_cmu_info *info; > + struct device *dev = &pdev->dev; > + > + info = of_device_get_match_data(dev); > + exynos_arm64_register_cmu(dev, dev->of_node, info); > + > + return 0; > +} > + > +static const struct of_device_id gs101_cmu_of_match[] = { > + { > + .compatible = "google,gs101-cmu-apm", > + .data = &apm_cmu_info, > + }, Missing terminating empty entry {}. Regards, Will > +}; > + > +static struct platform_driver gs101_cmu_driver __refdata = { > + .driver = { > + .name = "gs101-cmu", > + .of_match_table = gs101_cmu_of_match, > + .suppress_bind_attrs = true, > + }, > + .probe = gs101_cmu_probe, > +}; > + > +static int __init gs101_cmu_init(void) > +{ > + return platform_driver_register(&gs101_cmu_driver); > +} > +core_initcall(gs101_cmu_init); > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. It features: > * 4xA55 little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > > This commit adds the basic device tree for gs101 (SoC) and oriole > (pixel 6). Further platform support will be added over time. > > It has been tested with a minimal busybox initramfs and boots to > a shell. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > arch/arm64/Kconfig.platforms | 6 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/google/Makefile | 6 + > arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ > arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + > arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ > 7 files changed, 1733 insertions(+) > create mode 100644 arch/arm64/boot/dts/google/Makefile > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 6069120199bb..a5ed1b719488 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -107,6 +107,12 @@ config ARCH_EXYNOS > help > This enables support for ARMv8 based Samsung Exynos SoC family. > > +config ARCH_GOOGLE_TENSOR > + bool "Google Tensor SoC fmaily" > + depends on ARCH_EXYNOS > + help > + Support for ARMv8 based Google Tensor platforms. I'd like to bring up this thread and discuss the option of not introducing another ARCH_* config: https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ I especially don't like the "depends on ARCH_EXYNOS" because that forces one to include all the other Exynos drivers that ARCH_EXYNOS selects that Google Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all drivers that actually depend on the SoC hardware, we can just add "depends on SOC_GOOGLE"? The idea is that drivers should be tied to hardware -- not a specific vendor. By making drivers depend on ARCH_*, you are introducing an arbitrary vendor dependency and not a hardware dependency. Thanks, Will > + > config ARCH_SPARX5 > bool "Microchip Sparx5 SoC family" > select PINCTRL > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 30dd6347a929..a4ee7b628114 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -13,6 +13,7 @@ subdir-y += broadcom > subdir-y += cavium > subdir-y += exynos > subdir-y += freescale > +subdir-y += google > subdir-y += hisilicon > subdir-y += intel > subdir-y += lg > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile > new file mode 100644 > index 000000000000..6d2026a767d4 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/Makefile > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \ > + gs101-oriole.dtb \ > + > + > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts > new file mode 100644 > index 000000000000..e531a39a76a4 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts > @@ -0,0 +1,68 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Oriole DVT Device Tree > + * > + * Copyright 2021-2023 Google,LLC > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include "gs101-pinctrl.h" > +#include "gs101.dtsi" > + > +/ { > + model = "Oriole DVT"; > + compatible = "google,gs101-oriole", "google,gs101"; > +}; > + > +&pinctrl_1 { > + key_voldown: key-voldown-pins { > + samsung,pins = "gpa7-3"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + key_volup: key-volup-pins { > + samsung,pins = "gpa8-1"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_0 { > + key_power: key-power-pins { > + samsung,pins = "gpa10-1"; > + samsung,pin-function = <0xf>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&gpio_keys { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&key_voldown &key_volup &key_power>; > + button-vol-down { > + label = "KEY_VOLUMEDOWN"; > + linux,code = <114>; > + gpios = <&gpa7 3 0xf>; > + wakeup-source; > + }; > + button-vol-up { > + label = "KEY_VOLUMEUP"; > + linux,code = <115>; > + gpios = <&gpa8 1 0xf>; > + wakeup-source; > + }; > + button-power { > + label = "KEY_POWER"; > + linux,code = <116>; > + gpios = <&gpa10 1 0xf>; > + wakeup-source; > + }; > +}; > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > new file mode 100644 > index 000000000000..24825205ede8 > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > @@ -0,0 +1,1134 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC pin-mux and pin-config device tree source > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#include <dt-bindings/interrupt-controller/gs101.h> > +#include <arm64/exynos/exynos-pinctrl.h> > +#include "gs101-pinctrl.h" > + > +/ { > + /* GPIO_ALIVE */ > + pinctrl@174d0000 { > + gpa0: gpa0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>; > + }; > + gpa1: gpa1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>; > + }; > + gpa2: gpa2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>; > + }; > + gpa3: gpa3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>; > + }; > + gpa4: gpa4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>; > + }; > + gpa5: gpa5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>; > + }; > + gpa9: gpa9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>; > + }; > + gpa10: gpa10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>; > + }; > + > + uart15_bus: uart15-bus-pins { > + samsung,pins = "gpa2-3", "gpa2-4"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + > + uart16_bus: uart16-bus-pins { > + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + }; > + > + uart16_bus_rts: uart1-bus-rts-pins { > + samsung,pins = "gpa3-2"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-val = <1>; > + }; > + > + uart16_bus_tx_dat: uart1-bus-tx-dat-pins { > + samsung,pins = "gpa3-1"; > + samsung,pin-val = <1>; > + }; > + > + uart16_bus_tx_con: uart1-bus-tx-con-pins { > + samsung,pins = "gpa3-1"; > + samsung,pin-function = <1>; > + }; > + > + uart17_bus: uart17-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + > + spi15_bus: spi15-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi15_cs: spi15-cs-pins { > + samsung,pins = "gpa4-3"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + }; > + /* GPIO_FAR_ALIVE */ > + pinctrl@174e0000 { > + gpa6: gpa6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT46 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT47 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT48 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT49 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT50 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT51 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT52 ITLH>; > + }; > + gpa7: gpa7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT54 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT55 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT56 ITLH>; > + }; > + gpa8: gpa8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT58 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT59 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT60 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT61 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT62 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT63 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT64 ITLH>; > + }; > + gpa11: gpa11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>, > + <GIC_SPI IRQ_ALIVE_EINT66 ITLH>; > + }; > + > + }; > + /* GPIO_GSACORE */ > + pinctrl@17a80000 { > + gps0: gps0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gps1: gps1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gps2: gps2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + /* GPIO_GSACTRL */ > + pinctrl@17940000 { > + gps3: gps3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + /* GPIO_HSI1 */ > + pinctrl@11840000 { > + gph0: gph0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gph1: gph1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + pcie0_clkreq: pcie0-clkreq-pins{ > + samsung,pins = "gph0-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <3>; > + samsung,pin-pud-pdn = <3>; > + }; > + pcie0_perst: pcie0-perst-pins { > + samsung,pins = "gph0-0"; > + samsung,pin-function = <1>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <3>; > + }; > + }; > + /* GPIO_HSI2 */ > + pinctrl@14440000 { > + gph2: gph2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gph3: gph3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gph4: gph4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + sd2_clk: sd2-clk-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_cmd: sd2-cmd-pins { > + samsung,pins = "gph4-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus1: sd2-bus-width1-pins { > + samsung,pins = "gph4-2"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus4: sd2-bus-width4-pins { > + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + }; > + ufs_rst_n: ufs-rst-n-pins { > + samsung,pins = "gph3-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-con-pdn = <3>; > + samsung,pin-pud-pdn = <0>; > + }; > + > + ufs_refclk_out: ufs-refclk-out-pins { > + samsung,pins = "gph3-0"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-con-pdn = <3>; > + samsung,pin-pud-pdn = <0>; > + }; > + pcie1_clkreq: pcie1-clkreq-pins { > + samsung,pins = "gph2-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <3>; > + samsung,pin-pud-pdn = <3>; > + }; > + pcie1_perst: pcie1-perst-pins { > + samsung,pins = "gph2-0"; > + samsung,pin-function = <1>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <3>; > + }; > + }; > + /* GPIO_PERIC0 */ > + pinctrl@10840000 { > + gpp0: gpp0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp1: gpp1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp2: gpp2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp3: gpp3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp4: gpp4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp5: gpp5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp6: gpp6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp7: gpp7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp8: gpp8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp9: gpp9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp10: gpp10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp11: gpp11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp12: gpp12-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp13: gpp13-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp14: gpp14-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp15: gpp15-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp16: gpp16-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp17: gpp17-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp18: gpp18-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp19: gpp19-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + /* USI_PERIC0_UART_DBG */ > + uart0_bus: uart0-bus-pins { > + samsung,pins = "gpp1-2", "gpp1-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + > + disp_te_pri_on: disp-te-pri-on-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <0xf>; > + }; > + > + disp_te_pri_off: disp-te-pri-off-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <0>; > + }; > + > + disp_te_sec_on: disp-te-sec-on-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <0xf>; > + }; > + > + disp_te_sec_off: disp-te-sec-off-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <0>; > + }; > + > + sensor_mclk1_out: sensor-mclk1-out-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk1_fn: sensor-mclk1-fn-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk2_out: sensor-mclk2-out-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk2_fn: sensor-mclk2-fn-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk3_out: sensor-mclk3-out-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk3_fn: sensor-mclk3-fn-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk4_out: sensor-mclk4-out-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk4_fn: sensor-mclk4-fn-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk5_out: sensor-mclk5-out-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk5_fn: sensor-mclk5-fn-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk6_out: sensor-mclk6-out-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk6_fn: sensor-mclk6-fn-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk7_out: sensor-mclk7-out-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk7_fn: sensor-mclk7-fn-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk8_out: sensor-mclk8-out-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + sensor_mclk8_fn: sensor-mclk8-fn-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + hsi2c14_bus: hsi2c14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart14_bus_single: uart14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", > + "gpp18-2", "gpp18-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi14_bus: spi14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi14_cs: spi14-cs-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi14_cs_func: spi14-cs-func-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c8_bus: hsi2c8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>; > + }; > + uart8_bus_single: uart8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", > + "gpp16-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi8_bus: spi8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi8_cs: spi8-cs-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi8_cs_func: spi8-cs-func-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c7_bus: hsi2c7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart7_bus_single: uart7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", > + "gpp14-2", "gpp14-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi7_bus: spi7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi7_cs: spi7-cs-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi7_cs_func: spi7-cs-func-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c6_bus: hsi2c6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart6_bus_single: uart6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", > + "gpp12-2", "gpp12-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi6_bus: spi6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi6_cs: spi6-cs-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi6_cs_func: spi6-cs-func-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c5_bus: hsi2c5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart5_bus_single: uart5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", > + "gpp10-2", "gpp10-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi5_bus: spi5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; > + }; > + spi5_cs_func: spi5-cs-func-pins { > + samsung,pins = "gpp10-3"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; > + }; > + hsi2c4_bus: hsi2c4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart4_bus_single: uart4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", > + "gpp8-2", "gpp8-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi4_bus: spi4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi4_cs: spi4-cs-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi4_cs_func: spi4-cs-func-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c3_bus: hsi2c3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart3_bus_single: uart3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", > + "gpp6-2", "gpp6-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi3_bus: spi3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi3_cs: spi3-cs-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi3_cs_func: spi3-cs-func-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c2_bus: hsi2c2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart2_bus_single: uart2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", > + "gpp4-2", "gpp4-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi2_bus: spi2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi2_cs: spi2-cs-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi2_cs_func: spi2-cs-func-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c1_bus: hsi2c1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart1_bus_single: uart1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", > + "gpp2-2", "gpp2-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi1_bus: spi1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi1_cs: spi1-cs-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi1_cs_func: spi1-cs-func-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + }; > + /* GPIO_PERIC1 */ > + pinctrl@10c40000 { > + gpp20: gpp20-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp21: gpp21-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp22: gpp22-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp23: gpp23-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp24: gpp24-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp25: gpp25-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp26: gpp26-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + gpp27: gpp27-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + hsi2c13_bus: hsi2c13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart13_bus_single: uart13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", > + "gpp25-2", "gpp25-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi13_bus: spi13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi13_cs: spi13-cs-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi13_cs_func: spi13-cs-func-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c12_bus: hsi2c12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart12_bus_single: uart12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", > + "gpp23-6", "gpp23-7"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi12_bus: spi12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi14_cs2: spi14-cs2-pins { > + samsung,pins = "gpp23-6"; > + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi12_cs: spi12-cs-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi12_cs_func: spi12-cs-func-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c11_bus: hsi2c11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart11_bus_single: uart11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", > + "gpp23-2", "gpp23-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi11_bus: spi11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi11_cs: spi11-cs-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi11_cs_func: spi11-cs-func-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c10_bus: hsi2c10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart10_bus_single: uart10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", > + "gpp21-2", "gpp21-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi10_bus: spi10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi10_cs: spi10-cs-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi10_cs_func: spi10-cs-func-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c9_bus: hsi2c9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart9_bus_single: uart9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", > + "gpp20-6", "gpp20-7"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + }; > + spi9_bus: spi9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi9_cs: spi9-cs-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi9_cs_func: spi9-cs-func-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + hsi2c0_bus: hsi2c0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + uart0_bus_single: uart0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", > + "gpp20-2", "gpp20-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + }; > + spi0_bus: spi0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi0_cs: spi0-cs-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <1>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + spi0_cs_func: spi0-cs-func-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <3>; > + samsung,pin-pud = <0>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..acc77c684f0d > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright (c) 2020-2023 Google, LLC. > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi > new file mode 100644 > index 000000000000..0bd43745f6fa > --- /dev/null > +++ b/arch/arm64/boot/dts/google/gs101.dtsi > @@ -0,0 +1,501 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#include <dt-bindings/clock/gs101.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/gs101.h> > + > +#include "gs101-pinctrl.dtsi" > + > +/ { > + compatible = "google,gs101"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <1>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + pinctrl3 = &pinctrl_3; > + pinctrl4 = &pinctrl_4; > + pinctrl5 = &pinctrl_5; > + pinctrl6 = &pinctrl_6; > + pinctrl7 = &pinctrl_7; > + > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0000>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0100>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0200>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0300>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0400>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + cpu5: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0500>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + cpu6: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0600>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + cpu7: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0700>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + ANANKE_CPU_SLEEP: cpu-ananke-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <70>; > + exit-latency-us = <160>; > + min-residency-us = <2000>; > + status = "okay"; > + }; > + > + ENYO_CPU_SLEEP: cpu-enyo-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <150>; > + exit-latency-us = <190>; > + min-residency-us = <2500>; > + status = "okay"; > + }; > + > + HERA_CPU_SLEEP: cpu-hera-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <235>; > + exit-latency-us = <220>; > + min-residency-us = <3500>; > + status = "okay"; > + }; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + tpu_fw_reserved: tpu_fw@93000000 { > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss_log_reserved@fd3f0000 { > + reg = <0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 { > + reg = <0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr_log_reserved@fd800000 { > + reg = <0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 { > + reg = <0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + /* bootloader requires ect node */ > + ect { > + parameter_address = <0x90000000>; > + parameter_size = <0x53000>; > + }; > + > + chosen { > + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused"; > + }; > + > + gic: interrupt-controller@10400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x0 0x10400000 0x10000>, /* GICD */ > + <0x0 0x10440000 0x100000>; /* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <24576000>; > + }; > + > + ext_24_5m: ext_24_5m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24576000>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: ext_200m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + clock-output-names = "ext-200m"; > + }; > + > + /* GPIO_ALIVE */ > + pinctrl_0: pinctrl@174d0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x174d0000 0x00001000>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint"; > + }; > + }; > + > + /* GPIO_FAR_ALIVE */ > + pinctrl_1: pinctrl@174e0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x174e0000 0x00001000>; > + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint"; > + }; > + }; > + > + /* GPIO_GSACORE */ > + pinctrl_2: pinctrl@17a80000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x17a80000 0x00001000>; > + }; > + /* GPIO_GSACTRL */ > + pinctrl_3: pinctrl@17940000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x17940000 0x00001000>; > + }; > + /* GPIO_PERIC0 */ > + pinctrl_4: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x10840000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_PERIC1 */ > + pinctrl_5: pinctrl@10c40000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x10C40000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_HSI1 */ > + pinctrl_6: pinctrl@11840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x11840000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>; > + }; > + /* GPIO_HSI2 */ > + pinctrl_7: pinctrl@14440000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x00000000 0x14440000 0x00001000>; > + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + arm-pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + sysreg_apm: syscon@174204e0 { > + compatible = "google,gs101-apm-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x174204e0 0x1000>; > + }; > + > + sysreg_peric0: syscon@10821000 { > + compatible = "google,gs101-peric0-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x10821000 0x40000>; > + }; > + > + sysreg_peric1: syscon@10c21000 { > + compatible = "google,gs101-peric1-sysreg", > + "google,gs101-sysreg", "syscon"; > + reg = <0x0 0x10C21000 0x40000>; > + }; > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; > + clock-output-names = "pclk"; > + }; > + > + serial_0: serial@10a00000 { > + compatible = "samsung,exynos850-uart"; > + reg = <0x0 0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; > + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clock-names = "uart", "clk_uart_baud0"; > + status = "okay"; > + }; > + > + pmu_system_controller: system-controller@17460000 { > + compatible = "google,gs101-pmu", "syscon"; > + reg = <0x0 0x17460000 0x10000>; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x0 0x10060000 0x100>; > + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + timeout-sec = <30>; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + }; > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x0 0x10070000 0x100>; > + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + timeout-sec = <30>; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + cmu_top: clock-controller@1e080000 { > + compatible = "google,gs101-cmu-top"; > + reg = <0x0 0x1e080000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + > + cmu_apm: clock-controller@17400000 { > + compatible = "google,gs101-cmu-apm"; > + reg = <0x0 0x17400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x0 0x10010000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; > + clock-names = "oscclk", "dout_cmu_misc_bus"; > + }; > + > + dsu-pmu-0 { > + compatible = "arm,dsu-pmu"; > + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; > + > + gpio_keys: gpio_keys { > + compatible = "gpio-keys"; > + }; > + > +}; > -- > 2.42.0.582.g8ccd20d70d-goog >
On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar > to Exynos850 it has two watchdog instances, one for each cluster > and has some control bits in PMU registers. > > The watchdog IP found in gs101 SoCs also supports a few > additional bits/features in the WTCON register which we add > support for and an additional register detailed below. > > dbgack-mask - Enables masking WDT interrupt and reset request > according to asserted DBGACK input > > windowed-mode - Enabled Windowed watchdog mode > > Windowed watchdog mode also has an additional register WTMINCNT. > If windowed watchdog is enabled and you reload WTCNT when the > value is greater than WTMINCNT, it prompts interrupt or reset > request as if the watchdog time has expired. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++---- > 1 file changed, 105 insertions(+), 11 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..4c23c7e6a3f1 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -31,12 +31,14 @@ > #define S3C2410_WTDAT 0x04 > #define S3C2410_WTCNT 0x08 > #define S3C2410_WTCLRINT 0x0c > - > +#define S3C2410_WTMINCNT 0x10 > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > +#define S3C2410_WTCON_WINDOWED_WD (1 << 20) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -61,12 +63,16 @@ > #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520 > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544 > - > #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24 > #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > - > +#define GS_CLUSTER0_NONCPU_OUT 0x1220 > +#define GS_CLUSTER1_NONCPU_OUT 0x1420 > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 > +#define GS_RST_STAT_REG_OFFSET 0x3B44 > /** > * DOC: Quirk flags for different Samsung watchdog IP-cores > * > @@ -106,6 +112,8 @@ > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > +#define QUIRK_HAS_WTMINCNT_REG (1 << 6) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, > }; > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 0, > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > + .cnt_en_bit = 8, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 1, > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > + .cnt_en_bit = 7, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = { > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 0, > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > + .cnt_en_bit = 8, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = { > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 1, > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > + .cnt_en_bit = 7, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > static const struct of_device_id s3c2410_wdt_match[] = { > { .compatible = "samsung,s3c2410-wdt", > .data = &drv_data_s3c2410 }, > @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = { > .data = &drv_data_exynos850_cl0 }, > { .compatible = "samsung,exynosautov9-wdt", > .data = &drv_data_exynosautov9_cl0 }, > + { .compatible = "google,gs101-wdt", > + .data = &drv_data_gs101_cl0 }, > + { .compatible = "google,gs201-wdt", > + .data = &drv_data_gs201_cl0 }, > {}, > }; > MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); > @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + if (mask) > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + else > + wtcon &= ~S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > } > > #ifdef CONFIG_OF > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ > + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */ > if (variant == &drv_data_exynos850_cl0 || > - variant == &drv_data_exynosautov9_cl0) { > + variant == &drv_data_exynosautov9_cl0 || > + variant == &drv_data_gs101_cl0 || > + variant == &drv_data_gs201_cl0) { > u32 index; > int err; > > @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > case 0: > break; > case 1: > - variant = (variant == &drv_data_exynos850_cl0) ? > - &drv_data_exynos850_cl1 : > - &drv_data_exynosautov9_cl1; > + if (variant == &drv_data_exynos850_cl0) > + variant = &drv_data_exynos850_cl1; > + else if (variant == &drv_data_exynosautov9_cl0) > + variant = &drv_data_exynosautov9_cl1; > + else if (variant == &drv_data_gs101_cl0) > + variant = &drv_data_gs101_cl1; > + else if (variant == &drv_data_gs201_cl0) > + variant = &drv_data_gs201_cl1; > break; > default: > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); > @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt, true); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > s3c2410wdt_start(&wdt->wdt_device); > set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); > } else { > + dev_info(dev, "stopping watchdog timer\n"); I am not inclined to accept patches adding such noise. > s3c2410wdt_stop(&wdt->wdt_device); > } > > @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", > (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); > > + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT) > + dev_info(dev, "DBGACK %sabled\n", > + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis"); > + > + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) > + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n", > + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis", > + readl(wdt->reg_base + S3C2410_WTMINCNT)); ... and I really don't see its value. > + > return 0; > } > > -- > 2.42.0.582.g8ccd20d70d-goog >
On 05/10/2023 20:05, Greg KH wrote: > On Thu, Oct 05, 2023 at 10:59:12AM -0700, William McVicker wrote: >> On 10/05/2023, Peter Griffin wrote: >>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, >>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile >>> phones. It features: >>> * 4xA55 little cluster >>> * 2xA76 Mid cluster >>> * 2xX1 Big cluster >>> >>> This commit adds the basic device tree for gs101 (SoC) and oriole >>> (pixel 6). Further platform support will be added over time. >>> >>> It has been tested with a minimal busybox initramfs and boots to >>> a shell. >>> >>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> >>> --- >>> arch/arm64/Kconfig.platforms | 6 + >>> arch/arm64/boot/dts/Makefile | 1 + >>> arch/arm64/boot/dts/google/Makefile | 6 + >>> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + >>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ >>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + >>> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ >>> 7 files changed, 1733 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/google/Makefile >>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts >>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h >>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi >>> >>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms >>> index 6069120199bb..a5ed1b719488 100644 >>> --- a/arch/arm64/Kconfig.platforms >>> +++ b/arch/arm64/Kconfig.platforms >>> @@ -107,6 +107,12 @@ config ARCH_EXYNOS >>> help >>> This enables support for ARMv8 based Samsung Exynos SoC family. >>> >>> +config ARCH_GOOGLE_TENSOR >>> + bool "Google Tensor SoC fmaily" >>> + depends on ARCH_EXYNOS >>> + help >>> + Support for ARMv8 based Google Tensor platforms. >> >> I'd like to bring up this thread and discuss the option of not introducing >> another ARCH_* config: >> >> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ > > I agree, PLEASE don't add platform config options as that makes it > impossible to make a unified kernel image that works for more than one > platform at the same time. There is no single problem in making unified image as we were doing since beginning of ARM64. The ARCH_* is not a obstacle for this. > >> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to >> include all the other Exynos drivers that ARCH_EXYNOS selects that Google >> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all >> drivers that actually depend on the SoC hardware, we can just add "depends on >> SOC_GOOGLE"? > > Why do any of this at all? It should not be needed. > >> The idea is that drivers should be tied to hardware -- not a specific vendor. > > And drivers should be auto-loaded. > > All of these drivers are not vendor-specific at all, they are based on > the same IP blocks as others, so that is how they should be unified. They are vendor specific. All of them are specifically for Exynos hardwre, because this is Exynos. We call it Google GS/Tensor SoC just for fancy convenience, but this just Exynos. > >> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor >> dependency and not a hardware dependency. > > Totally agree, thanks for bringing this up. > Best regards, Krzysztof
On 05/10/2023 19:59, William McVicker wrote: > On 10/05/2023, Peter Griffin wrote: >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile >> phones. It features: >> * 4xA55 little cluster >> * 2xA76 Mid cluster >> * 2xX1 Big cluster >> >> This commit adds the basic device tree for gs101 (SoC) and oriole >> (pixel 6). Further platform support will be added over time. >> >> It has been tested with a minimal busybox initramfs and boots to >> a shell. >> >> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> >> --- >> arch/arm64/Kconfig.platforms | 6 + >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/google/Makefile | 6 + >> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + >> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ >> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + >> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ >> 7 files changed, 1733 insertions(+) >> create mode 100644 arch/arm64/boot/dts/google/Makefile >> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts >> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi >> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h >> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi >> >> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms >> index 6069120199bb..a5ed1b719488 100644 >> --- a/arch/arm64/Kconfig.platforms >> +++ b/arch/arm64/Kconfig.platforms >> @@ -107,6 +107,12 @@ config ARCH_EXYNOS >> help >> This enables support for ARMv8 based Samsung Exynos SoC family. >> >> +config ARCH_GOOGLE_TENSOR >> + bool "Google Tensor SoC fmaily" >> + depends on ARCH_EXYNOS >> + help >> + Support for ARMv8 based Google Tensor platforms. > > I'd like to bring up this thread and discuss the option of not introducing > another ARCH_* config: > > https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ > > I especially don't like the "depends on ARCH_EXYNOS" because that forces one to > include all the other Exynos drivers that ARCH_EXYNOS selects that Google Since we are creating unified kernel images, having other drivers is not a problem. > Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all SOC_GOOGLE will work exactly the same and depend on ARCH_EXYNOS or appear everywhere as ARCH_EXYNOS. We already had this talk with Tesla. > drivers that actually depend on the SoC hardware, we can just add "depends on > SOC_GOOGLE"? > > The idea is that drivers should be tied to hardware -- not a specific vendor. And hardware is Exynos. Tesla FSD and Google Tensor is Exynos, even if you do no like calling it. > By making drivers depend on ARCH_*, you are introducing an arbitrary vendor > dependency and not a hardware dependency. There is no arbitrary dependency. We call it all Exynos hardware, because this is Exynos. I remember what you were pushing for removal of ARCH_EXYNOS and there waas clear feedback, not only from me: this is against communities goals. > > Thanks, > Will Please trim the replies from unrelated context. Best regards, Krzysztof
On 05/10/2023 19:59, William McVicker wrote: > On 10/05/2023, Peter Griffin wrote: >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile >> phones. It features: >> * 4xA55 little cluster >> * 2xA76 Mid cluster >> * 2xX1 Big cluster >> >> This commit adds the basic device tree for gs101 (SoC) and oriole >> (pixel 6). Further platform support will be added over time. >> >> It has been tested with a minimal busybox initramfs and boots to >> a shell. >> William, Please do not Cc non-existing mailboxes. You added Cc kernel-team and we all got awesome bounces now: "We're writing to let you know that the group you tried to contact (kernel-team) may not exist, or you may not have permission to post messages to the group. A few more details on why you weren't able to post:" Best regards, Krzysztof
On 10/05/2023, Krzysztof Kozlowski wrote: > On 05/10/2023 19:59, William McVicker wrote: > > On 10/05/2023, Peter Griffin wrote: > >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > >> phones. It features: > >> * 4xA55 little cluster > >> * 2xA76 Mid cluster > >> * 2xX1 Big cluster > >> > >> This commit adds the basic device tree for gs101 (SoC) and oriole > >> (pixel 6). Further platform support will be added over time. > >> > >> It has been tested with a minimal busybox initramfs and boots to > >> a shell. > >> > > William, > > Please do not Cc non-existing mailboxes. You added Cc kernel-team and we > all got awesome bounces now: > > "We're writing to let you know that the group you tried to contact > (kernel-team) may not exist, or you may not have permission to post > messages to the group. A few more details on why you weren't able to post:" > > Best regards, > Krzysztof > Sorry, I mistyped the email. Should have been kernel-team@android.com. Regards, Will
On 05/10/2023 21:23, Greg KH wrote: > On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote: >>>> I'd like to bring up this thread and discuss the option of not introducing >>>> another ARCH_* config: >>>> >>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ >>> >>> I agree, PLEASE don't add platform config options as that makes it >>> impossible to make a unified kernel image that works for more than one >>> platform at the same time. >> >> There is no single problem in making unified image as we were doing >> since beginning of ARM64. The ARCH_* is not a obstacle for this. > > Then why are the ARCH_* options needed at all? What does this help out > with? It helps all the people and distros who do not want to build/package drivers or modules for unrelated hardware or architectures. Let's take Samsung Exynos UART driver. It will never, 100% never, work on x86, x86_64. There is no single need to package it for kernels build for these products. It will not work on nVidia Tegra ARM64, Qualcomm ARM64 SoC, so if you do not want to run on Exynos, then you do no select ARCH_EXYNOS and have significantly smaller image. Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS or SOC_GOOGLE serves only the purpose to allow distros and people customize build for specific hardware. It does not limit anyone on anything. > >>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to >>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google >>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all >>>> drivers that actually depend on the SoC hardware, we can just add "depends on >>>> SOC_GOOGLE"? >>> >>> Why do any of this at all? It should not be needed. >>> >>>> The idea is that drivers should be tied to hardware -- not a specific vendor. >>> >>> And drivers should be auto-loaded. >>> >>> All of these drivers are not vendor-specific at all, they are based on >>> the same IP blocks as others, so that is how they should be unified. >> >> They are vendor specific. All of them are specifically for Exynos >> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just >> for fancy convenience, but this just Exynos. > > Ok, then why is this ARCH_ option needed if these IP blocks really are > from something else and are part of other drivers? For the same reason above, because if I want to build kernel for Qualcomm, I want to drop easily anything not related. If I want to build kernel without I2C, I disable I2C bus which effectively disables all drivers which work on I2C. If I want to build kernel without Exynos, I disable ARCH_EXYNOS which effectively disables entire Exynos hardware. Think of SoC as a bus or interface. Best regards, Krzysztof
On 10/05/2023, Krzysztof Kozlowski wrote: > On 05/10/2023 21:23, Greg KH wrote: > > On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote: > >>>> I'd like to bring up this thread and discuss the option of not introducing > >>>> another ARCH_* config: > >>>> > >>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ > >>> > >>> I agree, PLEASE don't add platform config options as that makes it > >>> impossible to make a unified kernel image that works for more than one > >>> platform at the same time. > >> > >> There is no single problem in making unified image as we were doing > >> since beginning of ARM64. The ARCH_* is not a obstacle for this. > > > > Then why are the ARCH_* options needed at all? What does this help out > > with? > > It helps all the people and distros who do not want to build/package > drivers or modules for unrelated hardware or architectures. > > Let's take Samsung Exynos UART driver. It will never, 100% never, work > on x86, x86_64. There is no single need to package it for kernels build > for these products. It will not work on nVidia Tegra ARM64, Qualcomm > ARM64 SoC, so if you do not want to run on Exynos, then you do no select > ARCH_EXYNOS and have significantly smaller image. > > Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm > + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS > or SOC_GOOGLE serves only the purpose to allow distros and people > customize build for specific hardware. > > It does not limit anyone on anything. I'm glad you brought up Exynos UART because this is where one of the limitations is introduced. For example, if you want to modularize out all the vendor specific drivers from the core kernel to create a common arm64 kernel binary that works on all ARM64 devices, you will not be able to build in the early console UART drivers without enabling the respective ARCH_* configs. Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for debugging early boot issues. I understand that ARCH_* configs are used to selectively pick which device tree blobs are built, but forcing developers to pick all or nothing is where I have a problem. Regards, Will > > > > > > >>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to > >>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google > >>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all > >>>> drivers that actually depend on the SoC hardware, we can just add "depends on > >>>> SOC_GOOGLE"? > >>> > >>> Why do any of this at all? It should not be needed. > >>> > >>>> The idea is that drivers should be tied to hardware -- not a specific vendor. > >>> > >>> And drivers should be auto-loaded. > >>> > >>> All of these drivers are not vendor-specific at all, they are based on > >>> the same IP blocks as others, so that is how they should be unified. > >> > >> They are vendor specific. All of them are specifically for Exynos > >> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just > >> for fancy convenience, but this just Exynos. > > > > Ok, then why is this ARCH_ option needed if these IP blocks really are > > from something else and are part of other drivers? > > For the same reason above, because if I want to build kernel for > Qualcomm, I want to drop easily anything not related. If I want to build > kernel without I2C, I disable I2C bus which effectively disables all > drivers which work on I2C. If I want to build kernel without Exynos, I > disable ARCH_EXYNOS which effectively disables entire Exynos hardware. > > Think of SoC as a bus or interface. > > Best regards, > Krzysztof >
On 06/10/2023 01:19, William McVicker wrote: > On 10/05/2023, Krzysztof Kozlowski wrote: >> On 05/10/2023 21:23, Greg KH wrote: >>> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote: >>>>>> I'd like to bring up this thread and discuss the option of not introducing >>>>>> another ARCH_* config: >>>>>> >>>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ >>>>> >>>>> I agree, PLEASE don't add platform config options as that makes it >>>>> impossible to make a unified kernel image that works for more than one >>>>> platform at the same time. >>>> >>>> There is no single problem in making unified image as we were doing >>>> since beginning of ARM64. The ARCH_* is not a obstacle for this. >>> >>> Then why are the ARCH_* options needed at all? What does this help out >>> with? >> >> It helps all the people and distros who do not want to build/package >> drivers or modules for unrelated hardware or architectures. >> >> Let's take Samsung Exynos UART driver. It will never, 100% never, work >> on x86, x86_64. There is no single need to package it for kernels build >> for these products. It will not work on nVidia Tegra ARM64, Qualcomm >> ARM64 SoC, so if you do not want to run on Exynos, then you do no select >> ARCH_EXYNOS and have significantly smaller image. >> >> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm >> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS >> or SOC_GOOGLE serves only the purpose to allow distros and people >> customize build for specific hardware. >> >> It does not limit anyone on anything. > > I'm glad you brought up Exynos UART because this is where one of the > limitations is introduced. For example, if you want to modularize out all the > vendor specific drivers from the core kernel to create a common arm64 kernel > binary that works on all ARM64 devices, you will not be able to build in the > early console UART drivers without enabling the respective ARCH_* configs. When you build single kernel there is never need to NOT ENABLE respective ARCH configs. Please describe me upstream case for such need to NOT ENABLE. > Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for > debugging early boot issues. Really? How related? The drivers are independent. You describe some out-of-tree development process which we never needed for upstream work. And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > > I understand that ARCH_* configs are used to selectively pick which device tree > blobs are built, but forcing developers to pick all or nothing is where I have > a problem. No one forces you to pick up everything or nothing. You select ARCH_EXYNOS and still can drop all optional drivers. It's true you cannot drop mandatory drivers, but you are upstreaming Exynos platform, right? We do not talk about your out-of-tree Google work because it does not matter. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Add support for the pin-controller found on the gs101 > SoC used in Pixel 6 phones. > > The alive blocks on this SoC also have a filter selection > register. Add support for this so the digital or delay filter > can be selected. If the filter selection is not available > then the default filter (digital) is applied. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++- > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++ > 5 files changed, 302 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > index cb965cf93705..ae681725db26 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { > .ctrl = fsd_pin_ctrl, > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), > }; > + > +/* > + * bank type for non-alive type > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > + * (CONPDN bit field: 2, PUDPDN bit field: 4) > + */ > +static struct samsung_pin_bank_type bank_type_6 = { Bank types are defined at the top. "type_6" is way too vague. Look how the others are named. > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > +}; > + > +/* > + * bank type for alive type > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > + */ > +static const struct samsung_pin_bank_type bank_type_7 = { Same problem. > + .fld_width = { 4, 1, 4, 4, }, > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > +}; > + > +/* pin banks of gs101 pin-controller (ALIVE) */ > +static const struct samsung_pin_bank_data gs101_pin_alive[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE), > +}; > + > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE), > +}; > + > +/* pin banks of gs101 pin-controller (GSACORE) */ > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (GSACTRL) */ > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (PERIC0) */ > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (PERIC1) */ > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (HSI1) */ > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (HSI2) */ > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT), > +}; > + > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { > + { > + /* pin banks of gs101 pin-controller (ALIVE) */ > + .pin_banks = gs101_pin_alive, > + .nr_banks = ARRAY_SIZE(gs101_pin_alive), > + .eint_gpio_init = exynos_eint_gpio_init, > + .eint_wkup_init = exynos_eint_wkup_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ > + .pin_banks = gs101_pin_far_alive, > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), > + .eint_gpio_init = exynos_eint_gpio_init, > + .eint_wkup_init = exynos_eint_wkup_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (GSACORE) */ > + .pin_banks = gs101_pin_gsacore, > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), > + .eint_gpio_init = exynos_eint_gpio_init, > + }, { > + /* pin banks of gs101 pin-controller (GSACTRL) */ > + .pin_banks = gs101_pin_gsactrl, > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), > + .eint_gpio_init = exynos_eint_gpio_init, > + }, { > + /* pin banks of gs101 pin-controller (PERIC0) */ > + .pin_banks = gs101_pin_peric0, > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (PERIC1) */ > + .pin_banks = gs101_pin_peric1, > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (HSI1) */ > + .pin_banks = gs101_pin_hsi1, > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (HSI2) */ > + .pin_banks = gs101_pin_hsi2, > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, > +}; > + > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { > + .ctrl = gs101_pin_ctrl, > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), > +}; > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > index a8212fc126bf..0c6c3312abb7 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save { > u32 eint_mask; > }; Please split the patch into two: one of adding new filter code and second for new Google SoC. > > +static void exynos_eint_flt_config(int sel, int width, > + struct samsung_pinctrl_drv_data *d, > + struct samsung_pin_bank *bank) Arguments: first drv_data, then bank, then width, then sel... and what is sel actually? Also, why do you need width if it is always 0? Will it be different in next pinctrl controllers? So the filter is per entire bank? > +{ > + unsigned int flt_reg, flt_con = 0; > + unsigned int val, shift; > + int i; > + int loop_cnt; > + > + flt_con |= EXYNOS_FLTCON_EN; > + > + if (sel) > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL; > + > + flt_con |= EXYNOS_FLTCON_WIDTH(width); This is always 0, what's the point? > + > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > + > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > + /* > + * if nr_pins > 4, we should set FLTCON0 register fully. > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > + */ > + loop_cnt = 4; > + else > + loop_cnt = bank->nr_pins; Please document the layout of the registers in exynos_eint_flt_config() comment (not kerneldoc). Also document what do you want to achieve here - set entire bank to one filter for the suspend/resume? > + > + val = readl(d->virt_base + flt_reg); > + > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS_FLTCON_LEN; > + val &= ~(EXYNOS_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + > + writel(val, d->virt_base + flt_reg); > + Missing /* > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0. > + * (pin4 ~ ) > + */ > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > + writel(val, d->virt_base + flt_reg + 0x4); > +} > + > /* > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > * @d: driver data of samsung pinctrl driver. > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > goto err_domains; > } > > + /* Set Delay Analog Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > + 0, d, bank); > } > > return 0; > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > if (bank->eint_type != EINT_TYPE_WKUP) > continue; > > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > + 0, d, bank); > + > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > GFP_KERNEL); > if (!bank->irq_chip) { > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank( > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > struct exynos_irq_chip *irq_chip = NULL; > int i; > > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > if (bank->eint_type == EINT_TYPE_GPIO) > exynos_pinctrl_suspend_bank(drvdata, bank); > else if (bank->eint_type == EINT_TYPE_WKUP) { > + /* Setting Delay (Analog) Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > + 0, d, bank); > if (!irq_chip) { > irq_chip = bank->irq_chip; > irq_chip->set_eint_wakeup_mask(drvdata, > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank( > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > int i; > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > - if (bank->eint_type == EINT_TYPE_GPIO) > + if (bank->eint_type == EINT_TYPE_GPIO) { > exynos_pinctrl_resume_bank(drvdata, bank); > + } else if (bank->eint_type == EINT_TYPE_WKUP || > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > + 0, d, bank); > + } > } > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > index 7bd6d82c9f36..aafd8f9f52f8 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > @@ -16,6 +16,8 @@ > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H > #define __PINCTRL_SAMSUNG_EXYNOS_H > > +#include <linux/bitfield.h> > + I don't think you use in this header anything from bitfield. > /* Values for the pin CON register */ > #define EXYNOS_PIN_CON_FUNC_EINT 0xf > > @@ -50,6 +52,14 @@ > > #define EXYNOS_EINT_MAX_PER_BANK 8 > #define EXYNOS_EINT_NR_WKUP_EINT > +/* EINT filter configuration */ > +#define EXYNOS_FLTCON_EN BIT(7) EXYNOS9? Earlier variants did not have it, AFAIR. > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6) > +#define EXYNOS_FLTCON_SEL_DELAY 0 > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f) > +#define EXYNOS_FLTCON_MASK 0xFF Keep lowercase hex > +#define EXYNOS_FLTCON_LEN 8 > +#define EXYNOS_FLTCON_NR_PIN 4 > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > { \ > @@ -140,6 +150,40 @@ > .name = id \ > } Best regards, Krzysztof
On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > On 06/10/2023 01:19, William McVicker wrote: >> On 10/05/2023, Krzysztof Kozlowski wrote: >>> On 05/10/2023 21:23, Greg KH wrote: >> >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > valuable for >> debugging early boot issues. > > Really? How related? The drivers are independent. You describe some > out-of-tree development process which we never needed for upstream work. > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. Right: in general, all drivers are independent of the platform besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, but I think it's worth mentioning the known exceptions, so Greg and Will can take that fight to the respective places rather than discussing it in the platform submission: - Some subsystems are considered 'special' and the maintainers prefer the drivers to be automatically selected based on the ARCH_* settings instead of having user-visible options. This is traditionally true for large chunks of drivers/irqchip, drivers/clocksource and drivers/pinctrl, though it has gotten better over time on all of them. - Some older 32-bit platforms are still not as modular as we'd like them to be, especially the StrongARM (ARMv4) platforms that require a custom kernel build, and some of ARMv4T and ARMv5 boards that are still missing DT support. These tend to require drivers they directly link to from board code, so disabling the drivers would cause a link failure until this gets cleaned up. - A couple of drivers are force-enabled based on the ARCH_* options because booting without these drivers would risk permanent damage to hardware, e.g. in overtemp or overcurrent scenarios. - ACPI based platforms require the PCI host bridge driver to be built-in rather than a loadable module because ACPI needs to probe PCI devices during early boot. - Some subsystems (notably drivers/gpu/, but others as well) have an excessive number of 'select' statements, so you end up surprise-enabling a number of additional drivers and subsystems by enabling certain less important platform specific drivers. Arnd
Hi Krzysztof, Many thanks for reviewing the series :) On Thu, 5 Oct 2023 at 17:07, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:56, Peter Griffin wrote: > > GS101 has three different SYSREG controllers, add dedicated > > compatibles for them to the documentation. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > > index 163e912e9cad..02f580d6489b 100644 > > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > > @@ -50,6 +50,13 @@ properties: > > - samsung,exynosautov9-peric1-sysreg > > - const: samsung,exynosautov9-sysreg > > - const: syscon > > + - items: > > + - enum: > > + - google,gs101-peric0-sysreg > > + - google,gs101-peric1-sysreg > > + - google,gs101-apm-sysreg > > + - const: google,gs101-sysreg > > Please drop this one compatible. Exynos has it only for backwards > compatibility. Just double checking, you mean I should drop this one compatible? + - const: google,gs101-sysreg > > Also, please put entire list ("items") before such entry for > samsung,exynos5433-sysreg, so everything is more-or-less ordered > alphabetically, by the fallback compatible. Will do! regards, Peter
On 06/10/2023 14:41, Peter Griffin wrote: >>> + - enum: >>> + - google,gs101-peric0-sysreg >>> + - google,gs101-peric1-sysreg >>> + - google,gs101-apm-sysreg >>> + - const: google,gs101-sysreg >> >> Please drop this one compatible. Exynos has it only for backwards >> compatibility. > > Just double checking, you mean I should drop this one compatible? > + - const: google,gs101-sysreg Yes. Best regards, Krzysztof
On 10/06/2023, Arnd Bergmann wrote: > On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > > On 06/10/2023 01:19, William McVicker wrote: > >> On 10/05/2023, Krzysztof Kozlowski wrote: > >>> On 05/10/2023 21:23, Greg KH wrote: > >> > >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > > valuable for > >> debugging early boot issues. > > > > Really? How related? The drivers are independent. You describe some > > out-of-tree development process which we never needed for upstream work. > > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > > Right: in general, all drivers are independent of the platform > besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, > but I think it's worth mentioning the known exceptions, so Greg and > Will can take that fight to the respective places rather than > discussing it in the platform submission: > > - Some subsystems are considered 'special' and the maintainers > prefer the drivers to be automatically selected based on the > ARCH_* settings instead of having user-visible options. This is > traditionally true for large chunks of drivers/irqchip, > drivers/clocksource and drivers/pinctrl, though it has gotten > better over time on all of them. > > - Some older 32-bit platforms are still not as modular as we'd > like them to be, especially the StrongARM (ARMv4) platforms that > require a custom kernel build, and some of ARMv4T and ARMv5 > boards that are still missing DT support. These tend to require > drivers they directly link to from board code, so disabling > the drivers would cause a link failure until this gets > cleaned up. > > - A couple of drivers are force-enabled based on the ARCH_* > options because booting without these drivers would risk > permanent damage to hardware, e.g. in overtemp or overcurrent > scenarios. > > - ACPI based platforms require the PCI host bridge driver to > be built-in rather than a loadable module because ACPI > needs to probe PCI devices during early boot. > > - Some subsystems (notably drivers/gpu/, but others as well) > have an excessive number of 'select' statements, so you > end up surprise-enabling a number of additional drivers > and subsystems by enabling certain less important platform > specific drivers. > > Arnd So if the argument is that the existing upstream Exynos platforms are required to have these drivers built-in to the kernel to boot: COMMON_CLK_SAMSUNG CLKSRC_EXYNOS_MCT EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS EXYNOS_PMU PINCTRL PINCTRL_EXYNOS PM_GENERIC_DOMAINS if PM SOC_SAMSUNG ...then that is understandable and we can work to fix that. My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in the platform Kconfig? For example, I don't really like this: diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027..4c8f173c4dec 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and so on? How are we going to pick the right driver when we have a generic ARCH_GOOGLE_TENSOR config? Ideally, we should have one Exynos clock driver that can detect what hardware is running (using the DT) to determine what it needs to do. If you really want to compile out the other vendor's clock drivers using some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD configs (not ideal though). With that approach, we could drop the platform ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. Let me know your thoughts. Thanks, Will
On Thu, Oct 5, 2023 at 6:04 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 05/10/2023 17:55, Peter Griffin wrote: > > Add the gs101 SoC interrupt header that provides human readable > > constants for all the IRQs in the SoC. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > +#define ITNO IRQ_TYPE_NONE > > +#define ITER IRQ_TYPE_EDGE_RISING > > +#define ITEF IRQ_TYPE_EDGE_FALLING > > +#define ITEB IRQ_TYPE_EDGE_BOTH > > +#define ITLH IRQ_TYPE_LEVEL_HIGH > > +#define ITLL IRQ_TYPE_LEVEL_LOW > > No, these are not bindings. > > > + > > +#define IRQ_ALIVE_EINT0 0 > > +#define IRQ_ALIVE_EINT1 1 > > We do not keep interrupt numbers as bindings. Please drop entire file. Agree, but it should be fine to have as a SoC-specific .dtsi under arch/.../google/gs101-irq.dtsi though! Yours, Linus Walleij
On 06/10/2023 18:33, William McVicker wrote: > On 10/06/2023, Arnd Bergmann wrote: >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: >>> On 06/10/2023 01:19, William McVicker wrote: >>>> On 10/05/2023, Krzysztof Kozlowski wrote: >>>>> On 05/10/2023 21:23, Greg KH wrote: >>>> >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very >>> valuable for >>>> debugging early boot issues. >>> >>> Really? How related? The drivers are independent. You describe some >>> out-of-tree development process which we never needed for upstream work. >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. >> >> Right: in general, all drivers are independent of the platform >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, >> but I think it's worth mentioning the known exceptions, so Greg and >> Will can take that fight to the respective places rather than >> discussing it in the platform submission: >> >> - Some subsystems are considered 'special' and the maintainers >> prefer the drivers to be automatically selected based on the >> ARCH_* settings instead of having user-visible options. This is >> traditionally true for large chunks of drivers/irqchip, >> drivers/clocksource and drivers/pinctrl, though it has gotten >> better over time on all of them. >> >> - Some older 32-bit platforms are still not as modular as we'd >> like them to be, especially the StrongARM (ARMv4) platforms that >> require a custom kernel build, and some of ARMv4T and ARMv5 >> boards that are still missing DT support. These tend to require >> drivers they directly link to from board code, so disabling >> the drivers would cause a link failure until this gets >> cleaned up. >> >> - A couple of drivers are force-enabled based on the ARCH_* >> options because booting without these drivers would risk >> permanent damage to hardware, e.g. in overtemp or overcurrent >> scenarios. >> >> - ACPI based platforms require the PCI host bridge driver to >> be built-in rather than a loadable module because ACPI >> needs to probe PCI devices during early boot. >> >> - Some subsystems (notably drivers/gpu/, but others as well) >> have an excessive number of 'select' statements, so you >> end up surprise-enabling a number of additional drivers >> and subsystems by enabling certain less important platform >> specific drivers. >> >> Arnd > > So if the argument is that the existing upstream Exynos platforms are required > to have these drivers built-in to the kernel to boot: > COMMON_CLK_SAMSUNG > CLKSRC_EXYNOS_MCT > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS > EXYNOS_PMU > PINCTRL > PINCTRL_EXYNOS > PM_GENERIC_DOMAINS if PM > SOC_SAMSUNG > > ...then that is understandable and we can work to fix that. > > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in > the platform Kconfig? For example, I don't really like this: > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > index 76a494e95027..4c8f173c4dec 100644 > --- a/drivers/clk/samsung/Kconfig > +++ b/drivers/clk/samsung/Kconfig > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR > > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and > so on? Nothing happens... or happens anything you wish. Did you read the motivation why this was created like this? > How are we going to pick the right driver when e have a generic > ARCH_GOOGLE_TENSOR config? You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick is done by you. Nothing to do more. > Ideally, we should have one Exynos clock driver that > can detect what hardware is running (using the DT) to determine what it needs It's already like this. We're done. > to do. If you really want to compile out the other vendor's clock drivers using > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD Whether you call it SOC or ARCH it is the same. We organized it as ARCH. > configs (not ideal though). With that approach, we could drop the platform > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. There is no need for this. ARCH does exactly the same. Best regards, Krzysztof
Hi Krzysztof, Firstly, thankyou for all your reviews. It's much appreciated. On Fri, 6 Oct 2023 at 07:33, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:56, Peter Griffin wrote: > > Add support for the pin-controller found on the gs101 > > SoC used in Pixel 6 phones. > > > > The alive blocks on this SoC also have a filter selection > > register. Add support for this so the digital or delay filter > > can be selected. If the filter selection is not available > > then the default filter (digital) is applied. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++ > > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++- > > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++ > > 5 files changed, 302 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > index cb965cf93705..ae681725db26 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { > > .ctrl = fsd_pin_ctrl, > > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), > > }; > > + > > +/* > > + * bank type for non-alive type > > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > > + * (CONPDN bit field: 2, PUDPDN bit field: 4) > > + */ > > +static struct samsung_pin_bank_type bank_type_6 = { > > Bank types are defined at the top. "type_6" is way too vague. Look how > the others are named. Will fix > > > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > > +}; > > + > > +/* > > + * bank type for alive type > > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > > + */ > > +static const struct samsung_pin_bank_type bank_type_7 = { > > Same problem. Will fix > > > + .fld_width = { 4, 1, 4, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > +}; > > + > > +/* pin banks of gs101 pin-controller (ALIVE) */ > > +static const struct samsung_pin_bank_data gs101_pin_alive[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE), > > +}; > > + > > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ > > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE), > > +}; > > + > > +/* pin banks of gs101 pin-controller (GSACORE) */ > > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (GSACTRL) */ > > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (PERIC0) */ > > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (PERIC1) */ > > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (HSI1) */ > > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (HSI2) */ > > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT), > > +}; > > + > > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { > > + { > > + /* pin banks of gs101 pin-controller (ALIVE) */ > > + .pin_banks = gs101_pin_alive, > > + .nr_banks = ARRAY_SIZE(gs101_pin_alive), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ > > + .pin_banks = gs101_pin_far_alive, > > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (GSACORE) */ > > + .pin_banks = gs101_pin_gsacore, > > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + }, { > > + /* pin banks of gs101 pin-controller (GSACTRL) */ > > + .pin_banks = gs101_pin_gsactrl, > > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + }, { > > + /* pin banks of gs101 pin-controller (PERIC0) */ > > + .pin_banks = gs101_pin_peric0, > > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (PERIC1) */ > > + .pin_banks = gs101_pin_peric1, > > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (HSI1) */ > > + .pin_banks = gs101_pin_hsi1, > > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (HSI2) */ > > + .pin_banks = gs101_pin_hsi2, > > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, > > +}; > > + > > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { > > + .ctrl = gs101_pin_ctrl, > > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), > > +}; > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index a8212fc126bf..0c6c3312abb7 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save { > > u32 eint_mask; > > }; > > Please split the patch into two: one of adding new filter code and > second for new Google SoC. Will do > > > > > +static void exynos_eint_flt_config(int sel, int width, > > + struct samsung_pinctrl_drv_data *d, > > + struct samsung_pin_bank *bank) > > Arguments: first drv_data, then bank, then width, then sel... and what > is sel actually? Will fix. Sel parameter is just setting the FLT_SEL bitfield 0 = Delay filter 1 = Digital filter > > Also, why do you need width if it is always 0? Will it be different in > next pinctrl controllers? The downstream driver never set the width bitfield so I we could remove this width logic and add it back if it's ever required. > So the filter is per entire bank? The filter is selectable per pin. So each pin has a FLT_EN, FLT_SEL and FLT_WIDTH bitfield. > > > +{ > > + unsigned int flt_reg, flt_con = 0; > > + unsigned int val, shift; > > + int i; > > + int loop_cnt; > > + > > + flt_con |= EXYNOS_FLTCON_EN; > > + > > + if (sel) > > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL; > > + > > + flt_con |= EXYNOS_FLTCON_WIDTH(width); > > This is always 0, what's the point? Yeah we could remove this, and add it back if it's ever required. Let me know if that's what you prefer? > > > + > > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > + > > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > > + /* > > + * if nr_pins > 4, we should set FLTCON0 register fully. > > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > > + */ > > + loop_cnt = 4; > > + else > > + loop_cnt = bank->nr_pins; > > Please document the layout of the registers in exynos_eint_flt_config() > comment (not kerneldoc). Also document what do you want to achieve here > - set entire bank to one filter for the suspend/resume? Yes exactly it is looping through setting all the pins in the bank to one filter on suspend and resume. I will add a comment as you suggest. > > > + > > + val = readl(d->virt_base + flt_reg); > > + > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS_FLTCON_LEN; > > + val &= ~(EXYNOS_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + > > + writel(val, d->virt_base + flt_reg); > > + > > Missing /* Will fix > > > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0. > > + * (pin4 ~ ) > > + */ > > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > > + writel(val, d->virt_base + flt_reg + 0x4); > > +} > > + > > /* > > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > > * @d: driver data of samsung pinctrl driver. > > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > > goto err_domains; > > } > > > > + /* Set Delay Analog Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > > + 0, d, bank); > > } > > > > return 0; > > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > > if (bank->eint_type != EINT_TYPE_WKUP) > > continue; > > > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > > + 0, d, bank); > > + > > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > > GFP_KERNEL); > > if (!bank->irq_chip) { > > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank( > > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > struct exynos_irq_chip *irq_chip = NULL; > > int i; > > > > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > if (bank->eint_type == EINT_TYPE_GPIO) > > exynos_pinctrl_suspend_bank(drvdata, bank); > > else if (bank->eint_type == EINT_TYPE_WKUP) { > > + /* Setting Delay (Analog) Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > > + 0, d, bank); > > if (!irq_chip) { > > irq_chip = bank->irq_chip; > > irq_chip->set_eint_wakeup_mask(drvdata, > > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank( > > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > int i; > > > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > > - if (bank->eint_type == EINT_TYPE_GPIO) > > + if (bank->eint_type == EINT_TYPE_GPIO) { > > exynos_pinctrl_resume_bank(drvdata, bank); > > + } else if (bank->eint_type == EINT_TYPE_WKUP || > > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > > + 0, d, bank); > > + } > > } > > > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > > index 7bd6d82c9f36..aafd8f9f52f8 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > > @@ -16,6 +16,8 @@ > > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H > > #define __PINCTRL_SAMSUNG_EXYNOS_H > > > > +#include <linux/bitfield.h> > > + > > I don't think you use in this header anything from bitfield. > > > /* Values for the pin CON register */ > > #define EXYNOS_PIN_CON_FUNC_EINT 0xf > > > > @@ -50,6 +52,14 @@ > > > > #define EXYNOS_EINT_MAX_PER_BANK 8 > > #define EXYNOS_EINT_NR_WKUP_EINT > > +/* EINT filter configuration */ > > +#define EXYNOS_FLTCON_EN BIT(7) > > EXYNOS9? Earlier variants did not have it, AFAIR. Will fix > > > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6) > > +#define EXYNOS_FLTCON_SEL_DELAY 0 > > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f) > > +#define EXYNOS_FLTCON_MASK 0xFF > > Keep lowercase hex Will fix Kind regards, Peter.
On 05/10/2023 17:55, Peter Griffin wrote: > Hi folks, > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > Currently DT is just added for the gs101 SoC and Oriole. > > The support added in this series consists of: > * cpus > * pinctrl > * some CCF clock implementation > * watchdog > * uart > * gpio Hi Peter, Heads up, in case you are not aware Arm SoC timeframes: we are at rc5, so it means that anything targeting v6.7 should be applied this working week, before rc6. At least as ARM SoC is concerned. Best regards, Krzysztof
Hi Krzysztof, On Thu, 5 Oct 2023 at 17:32, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:55, Peter Griffin wrote: > > Hi folks, > > > > This series adds initial SoC support for the GS101 SoC and also initial board > > support for Pixel 6 phone (Oriole). > > > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > > Currently DT is just added for the gs101 SoC and Oriole. > > Thanks for submitting the patches. Nice work! Thanks, and thankyou for reviewing the series so promptly. > > This is basically a custom-made variant of Exynos made by Samsung for > Google. Something similar what is with Tesla FSD (and Axis Artpec-8 > which was not upstreamed, AFAIR). Many, many drivers and bindings will > be re-used. I want to be sure that GS101 fits into existing Samsung > Exynos support, re-uses it as much as possible and extend when necessary > without breaking anything. Therefore, when the patches are ready, I > would like to be the one applying entire set and future submissions > through Samsung SoC tree, just like I am doing it with Tesla FSD, so I > keep entire Samsung-ecosystem in shape. > > This also means that you are lucky to be selected to: > https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst > joining there Tesla FSD and entire Samsung Exynos family :) > > I hope that's ok. That's all fine, it makes sense and it was what I was expecting. Maybe we can try and get you some Pixel 6 hardware as well. The only other Exynos hardware I have for testing unfortunately is the e850 board Sam has been working on. Coincidentally https://www.crowdsupply.com/0xda/usb-cereal just started shipping. Which is quite nice (albeit coincidental) timing, as anyone who has a Pixel 6 device can order one so they can run upstream kernels on their phone and have the debug UART available (which currently is the only way to really interact with the system until we bring up more IO). regards, Peter
Hi Krzysztof, On Mon, 9 Oct 2023 at 12:10, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:55, Peter Griffin wrote: > > Hi folks, > > > > This series adds initial SoC support for the GS101 SoC and also initial board > > support for Pixel 6 phone (Oriole). > > > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > > Currently DT is just added for the gs101 SoC and Oriole. > > > > The support added in this series consists of: > > * cpus > > * pinctrl > > * some CCF clock implementation > > * watchdog > > * uart > > * gpio > > Hi Peter, > > Heads up, in case you are not aware Arm SoC timeframes: we are at rc5, > so it means that anything targeting v6.7 should be applied this working > week, before rc6. At least as ARM SoC is concerned. Thanks for the heads up! I'm just working on v2 now incorporating all the review feedback. I'm hoping to have that sent out by the end of today or early tomorrow. Thanks, Peter.
Hi Guenter, On Thu, 5 Oct 2023 at 19:58, Guenter Roeck <linux@roeck-us.net> wrote: > > On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote: > > This patch adds the compatibles and drvdata for the Google > > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar > > to Exynos850 it has two watchdog instances, one for each cluster > > and has some control bits in PMU registers. > > > > The watchdog IP found in gs101 SoCs also supports a few > > additional bits/features in the WTCON register which we add > > support for and an additional register detailed below. > > > > dbgack-mask - Enables masking WDT interrupt and reset request > > according to asserted DBGACK input > > > > windowed-mode - Enabled Windowed watchdog mode > > > > Windowed watchdog mode also has an additional register WTMINCNT. > > If windowed watchdog is enabled and you reload WTCNT when the > > value is greater than WTMINCNT, it prompts interrupt or reset > > request as if the watchdog time has expired. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++---- > > 1 file changed, 105 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > > index 0b4bd883ff28..4c23c7e6a3f1 100644 > > --- a/drivers/watchdog/s3c2410_wdt.c > > +++ b/drivers/watchdog/s3c2410_wdt.c > > @@ -31,12 +31,14 @@ > > #define S3C2410_WTDAT 0x04 > > #define S3C2410_WTCNT 0x08 > > #define S3C2410_WTCLRINT 0x0c > > - > > +#define S3C2410_WTMINCNT 0x10 > > #define S3C2410_WTCNT_MAXCNT 0xffff > > > > -#define S3C2410_WTCON_RSTEN (1 << 0) > > -#define S3C2410_WTCON_INTEN (1 << 2) > > -#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_RSTEN (1 << 0) > > +#define S3C2410_WTCON_INTEN (1 << 2) > > +#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > +#define S3C2410_WTCON_WINDOWED_WD (1 << 20) > > > > #define S3C2410_WTCON_DIV16 (0 << 3) > > #define S3C2410_WTCON_DIV32 (1 << 3) > > @@ -61,12 +63,16 @@ > > #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 > > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520 > > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544 > > - > > #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24 > > #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 > > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > > - > > +#define GS_CLUSTER0_NONCPU_OUT 0x1220 > > +#define GS_CLUSTER1_NONCPU_OUT 0x1420 > > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 > > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 > > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 > > +#define GS_RST_STAT_REG_OFFSET 0x3B44 > > /** > > * DOC: Quirk flags for different Samsung watchdog IP-cores > > * > > @@ -106,6 +112,8 @@ > > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > +#define QUIRK_HAS_WTMINCNT_REG (1 << 6) > > > > /* These quirks require that we have a PMU register map */ > > #define QUIRKS_HAVE_PMUREG \ > > @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { > > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, > > }; > > > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { > > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > > + .mask_bit = 2, > > + .mask_reset_inv = true, > > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > > + .rst_stat_bit = 0, > > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > > + .cnt_en_bit = 8, > > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > > +}; > > + > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { > > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > > + .mask_bit = 2, > > + .mask_reset_inv = true, > > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > > + .rst_stat_bit = 1, > > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > > + .cnt_en_bit = 7, > > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > > +}; > > + > > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = { > > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > > + .mask_bit = 2, > > + .mask_reset_inv = true, > > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > > + .rst_stat_bit = 0, > > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > > + .cnt_en_bit = 8, > > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > > +}; > > + > > +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = { > > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > > + .mask_bit = 2, > > + .mask_reset_inv = true, > > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > > + .rst_stat_bit = 1, > > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > > + .cnt_en_bit = 7, > > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > > +}; > > + > > static const struct of_device_id s3c2410_wdt_match[] = { > > { .compatible = "samsung,s3c2410-wdt", > > .data = &drv_data_s3c2410 }, > > @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = { > > .data = &drv_data_exynos850_cl0 }, > > { .compatible = "samsung,exynosautov9-wdt", > > .data = &drv_data_exynosautov9_cl0 }, > > + { .compatible = "google,gs101-wdt", > > + .data = &drv_data_gs101_cl0 }, > > + { .compatible = "google,gs201-wdt", > > + .data = &drv_data_gs201_cl0 }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); > > @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > > return 0; > > } > > > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask) > > +{ > > + unsigned long wtcon; > > + > > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > > + return; > > + > > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > > + if (mask) > > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > > + else > > + wtcon &= ~S3C2410_WTCON_DBGACK_MASK; > > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > > +} > > + > > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > > { > > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > > @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > > } > > > > #ifdef CONFIG_OF > > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ > > + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */ > > if (variant == &drv_data_exynos850_cl0 || > > - variant == &drv_data_exynosautov9_cl0) { > > + variant == &drv_data_exynosautov9_cl0 || > > + variant == &drv_data_gs101_cl0 || > > + variant == &drv_data_gs201_cl0) { > > u32 index; > > int err; > > > > @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > > case 0: > > break; > > case 1: > > - variant = (variant == &drv_data_exynos850_cl0) ? > > - &drv_data_exynos850_cl1 : > > - &drv_data_exynosautov9_cl1; > > + if (variant == &drv_data_exynos850_cl0) > > + variant = &drv_data_exynos850_cl1; > > + else if (variant == &drv_data_exynosautov9_cl0) > > + variant = &drv_data_exynosautov9_cl1; > > + else if (variant == &drv_data_gs101_cl0) > > + variant = &drv_data_gs101_cl1; > > + else if (variant == &drv_data_gs201_cl0) > > + variant = &drv_data_gs201_cl1; > > break; > > default: > > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); > > @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > > wdt->wdt_device.parent = dev; > > > > + s3c2410wdt_mask_dbgack(wdt, true); > > + > > /* > > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > > @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > s3c2410wdt_start(&wdt->wdt_device); > > set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); > > } else { > > + dev_info(dev, "stopping watchdog timer\n"); > > I am not inclined to accept patches adding such noise. > > > s3c2410wdt_stop(&wdt->wdt_device); > > } > > > > @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", > > (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); > > > > + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT) > > + dev_info(dev, "DBGACK %sabled\n", > > + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis"); > > + > > + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) > > + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n", > > + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis", > > + readl(wdt->reg_base + S3C2410_WTMINCNT)); > > ... and I really don't see its value. Thanks for your review feedback. I will remove these dev_info prints in v2. regards, Peter.
On 10/07/2023, Krzysztof Kozlowski wrote: > On 06/10/2023 18:33, William McVicker wrote: > > On 10/06/2023, Arnd Bergmann wrote: > >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > >>> On 06/10/2023 01:19, William McVicker wrote: > >>>> On 10/05/2023, Krzysztof Kozlowski wrote: > >>>>> On 05/10/2023 21:23, Greg KH wrote: > >>>> > >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > >>> valuable for > >>>> debugging early boot issues. > >>> > >>> Really? How related? The drivers are independent. You describe some > >>> out-of-tree development process which we never needed for upstream work. > >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > >> > >> Right: in general, all drivers are independent of the platform > >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, > >> but I think it's worth mentioning the known exceptions, so Greg and > >> Will can take that fight to the respective places rather than > >> discussing it in the platform submission: > >> > >> - Some subsystems are considered 'special' and the maintainers > >> prefer the drivers to be automatically selected based on the > >> ARCH_* settings instead of having user-visible options. This is > >> traditionally true for large chunks of drivers/irqchip, > >> drivers/clocksource and drivers/pinctrl, though it has gotten > >> better over time on all of them. > >> > >> - Some older 32-bit platforms are still not as modular as we'd > >> like them to be, especially the StrongARM (ARMv4) platforms that > >> require a custom kernel build, and some of ARMv4T and ARMv5 > >> boards that are still missing DT support. These tend to require > >> drivers they directly link to from board code, so disabling > >> the drivers would cause a link failure until this gets > >> cleaned up. > >> > >> - A couple of drivers are force-enabled based on the ARCH_* > >> options because booting without these drivers would risk > >> permanent damage to hardware, e.g. in overtemp or overcurrent > >> scenarios. > >> > >> - ACPI based platforms require the PCI host bridge driver to > >> be built-in rather than a loadable module because ACPI > >> needs to probe PCI devices during early boot. > >> > >> - Some subsystems (notably drivers/gpu/, but others as well) > >> have an excessive number of 'select' statements, so you > >> end up surprise-enabling a number of additional drivers > >> and subsystems by enabling certain less important platform > >> specific drivers. > >> > >> Arnd > > > > So if the argument is that the existing upstream Exynos platforms are required > > to have these drivers built-in to the kernel to boot: > > COMMON_CLK_SAMSUNG > > CLKSRC_EXYNOS_MCT > > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS > > EXYNOS_PMU > > PINCTRL > > PINCTRL_EXYNOS > > PM_GENERIC_DOMAINS if PM > > SOC_SAMSUNG > > > > ...then that is understandable and we can work to fix that. > > > > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in > > the platform Kconfig? For example, I don't really like this: > > > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > > index 76a494e95027..4c8f173c4dec 100644 > > --- a/drivers/clk/samsung/Kconfig > > +++ b/drivers/clk/samsung/Kconfig > > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR > > > > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and > > so on? > > Nothing happens... or happens anything you wish. Did you read the > motivation why this was created like this? > > > > How are we going to pick the right driver when e have a generic > > ARCH_GOOGLE_TENSOR config? > Okay, we can figure that out the gs201 specifics when the time comes. > You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick > is done by you. Nothing to do more. > > > Ideally, we should have one Exynos clock driver that > > can detect what hardware is running (using the DT) to determine what it needs > > It's already like this. We're done. > > > to do. If you really want to compile out the other vendor's clock drivers using > > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD > > Whether you call it SOC or ARCH it is the same. We organized it as ARCH. > > > configs (not ideal though). With that approach, we could drop the platform > > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for > > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. > > There is no need for this. ARCH does exactly the same. Okay, sounds good. Thanks for the responses. Regards, Will > > Best regards, > Krzysztof >
Hi folks, This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). Currently DT is just added for the gs101 SoC and Oriole. The support added in this series consists of: * cpus * pinctrl * some CCF clock implementation * watchdog * uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. Currently we boot with clk_ignore_unused parameter but this will be updated as more clocks and platform support lands. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts I've also included the dtbo overlay containing board_id and board_rev in this series as otherwise the LK bootloader will bootloop if this is not present in the dtbo partition. It seems like it would be nicer for the upstream kernel to build all the DT required to boot upstream kernel on a production phone rather than having to obtain this dtbo from some other place, but if it is a pain point then I can remove it. Many thanks, Peter. Peter Griffin (21): dt-bindings: interrupt-controller: Add gs101 interrupt controller dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: clock: gs101: Add cmu_top clock indices dt-bindings: clock: gs101: Add cmu_apm clock indices dt-bindings: clock: gs101: Add cmu_misc clock indices clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates clk: samsung: clk-gs101: add CMU_APM support clk: google: gs101: Add support for CMU_MISC clock unit pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for Google tensor SoCs arm64: dts: google: Add initial Google gs101 SoC support google/gs101: Add dt overlay for oriole board arm64: defconfig: Enable Google Tensor SoC MAINTAINERS: add entry for Google Tensor SoC .../devicetree/bindings/arm/google.yaml | 46 + .../bindings/clock/google,gs101-clock.yaml | 109 + .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + .../bindings/pinctrl/samsung,pinctrl.yaml | 4 +- .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../soc/samsung/samsung,exynos-sysreg.yaml | 7 + .../bindings/watchdog/samsung-wdt.yaml | 10 +- MAINTAINERS | 11 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 7 + arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 + arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++ arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/samsung/Kconfig | 9 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2171 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 9 +- drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 44 + drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + drivers/watchdog/s3c2410_wdt.c | 116 +- include/dt-bindings/clock/gs101.h | 232 ++ .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++ 30 files changed, 5533 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/google/Makefile create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/gs101.h create mode 100644 include/dt-bindings/interrupt-controller/gs101.h