[v2,28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC

Message ID	20230929053915.1530607-29-claudiu.beznea@bp.renesas.com
State	New
Headers	show Return-Path: <linux-serial-owner@vger.kernel.org> From: Claudiu <claudiu.beznea@tuxon.dev> To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC Date: Fri, 29 Sep 2023 08:39:15 +0300 Message-Id: <20230929053915.1530607-29-claudiu.beznea@bp.renesas.com> In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK \| expand [v2,00/28] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK [v2,01/28] dt-bindings: serial: renesas,scif: document r9a08g045 support [v2,02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing [v2,03/28] clk: renesas: rzg2l: lock around writes to mux register [v2,04/28] clk: renesas: rzg2l: trust value returned by hardware [v2,05/28] clk: renesas: rzg2l: fix computation formula [v2,06/28] clk: renesas: rzg2l: remove critical area [v2,07/28] clk: renesas: rzg2l: add support for RZ/G3S PLL [v2,08/28] clk: renesas: rzg2l: add struct clk_hw_data [v2,09/28] clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header [v2,10/28] clk: renesas: rzg2l: refactor sd mux driver [v2,11/28] clk: renesas: rzg2l: add a divider clock for RZ/G3S [v2,12/28] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC [v2,13/28] clk: renesas: add minimal boot support for RZ/G3S SoC [v2,14/28] pinctrl: renesas: rzg2l: index all registers based on port offset [v2,15/28] pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets [v2,16/28] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S [v2,17/28] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration [v2,18/28] pinctrl: renesas: rzg2l: add support for different ds values on different groups [v2,19/28] dt-bindings: pinctrl: renesas: set additionalProperties: false [v2,20/28] dt-bindings: pinctrl: renesas: document RZ/G3S SoC [v2,21/28] pinctrl: renesas: rzg2l: add support for RZ/G3S SoC [v2,22/28] arm64: dts: renesas: add initial DTSI for RZ/G3S SoC [v2,23/28] dt-bindings: arm: renesas: document RZ/G3S SMARC SoM [v2,24/28] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC SoM [v2,25/28] arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II Board [v2,26/28] dt-bindings: arm: renesas: document SMARC Carrier-II EVK [v2,27/28] arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK ... [v2,28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC

Message ID

20230929053915.1530607-29-claudiu.beznea@bp.renesas.com

State

New

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, linus.walleij@linaro.org,
        gregkh@linuxfoundation.org, jirislaby@kernel.org,
        magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org,
        quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de,
        neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
        biju.das.jz@bp.renesas.com
Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC
Date: Fri, 29 Sep 2023 08:39:15 +0300
Message-Id: <20230929053915.1530607-29-claudiu.beznea@bp.renesas.com>
In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com>
References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK | expand

Commit Message

Claudiu Sept. 29, 2023, 5:39 a.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable config flag for Renesas RZ/G3S (R9A08G045) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

Changes in v2:
- collected tags

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

Comments

Geert Uytterhoeven Oct. 4, 2023, 1:34 p.m. UTC | #1

On Fri, Sep 29, 2023 at 7:40 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Enable config flag for Renesas RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>
> Changes in v2:
> - collected tags

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.7.

Gr{oetje,eeting}s,

                        Geert

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 66bfbef73324..07011114eef8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1341,6 +1341,7 @@  CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R9A07G043=y
 CONFIG_ARCH_R9A07G044=y
 CONFIG_ARCH_R9A07G054=y
+CONFIG_ARCH_R9A08G045=y
 CONFIG_ARCH_R9A09G011=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y

[v2,28/28] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC

Commit Message

Comments

Patch