| Message ID | 20230829135818.2219438-1-quic_ipkumar@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable USB3 for IPQ5332 | expand |
On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Add ipq5332 USB3 SS UNIPHY support. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- > 1 file changed, 114 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > index cbe2cc820009..17ba661b3d9b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > @@ -19,21 +19,53 @@ properties: > enum: > - qcom,usb-ss-ipq4019-phy > - qcom,usb-hs-ipq4019-phy > + - qcom,ipq5332-usb-ssphy > > reg: > maxItems: 1 > > + reg-names: > + items: > + - const: phy_base > + > + clocks: > + maxItems: 3 > + > + clock-names: > + maxItems: 3 > + > + "#clock-cells": > + const: 0 > + > resets: > + minItems: 1 > maxItems: 2 > > reset-names: > - items: > - - const: por_rst > - - const: srif_rst > + minItems: 1 > + maxItems: 2 > + > + clock-output-names: > + maxItems: 1 > > "#phy-cells": > const: 0 > > + qcom,phy-mux-sel: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + PHY Mux Selection for used to select which interface is going to use the > + combo PHY. > + items: > + - items: > + - description: phandle to TCSR syscon region > + - description: offset to the PHY Mux selection register > + - description: value to write on the PHY Mux selection register Generally these values should be a part of the driver, since they are specific to the particular SoC, rather than being different from device to device. > + > + vdd-supply: > + description: > + Phandle to 5V regulator supply to PHY digital circuit. > + > required: > - compatible > - reg > @@ -41,6 +73,68 @@ required: > - reset-names > - "#phy-cells" > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,ipq5332-usb-ssphy > + then: > + properties: > + clocks: > + maxItems: 3 > + clock-names: > + items: > + - const: pipe > + - const: phy_cfg_ahb > + - const: phy_ahb > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: por_rst > + > + vdda-supply: > + description: > + Phandle to 5V regulator supply to PHY digital circuit. > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,usb-ss-ipq4019-phy > + then: > + properties: > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: por_rst > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,usb-hs-ipq4019-phy > + then: > + properties: > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: por_rst > + - const: srif_rst > + > additionalProperties: false > > examples: > @@ -55,3 +149,20 @@ examples: > <&gcc USB2_HSPHY_S_ARES>; > reset-names = "por_rst", "srif_rst"; > }; > + > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + > + ssuniphy@4b0000 { > + #phy-cells = <0>; > + #clock-cells = <0>; > + compatible = "qcom,ipq5332-usb-ssphy"; > + reg = <0x4b0000 0x800>; > + clocks = <&gcc GCC_USB0_PIPE_CLK>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; > + clock-names = "pipe", "phy_cfg_ahb", "phy_ahb"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>; > + reset-names = "por_rst"; > + }; > -- > 2.34.1 >
On Tue, 29 Aug 2023 19:28:13 +0530, Praveenkumar I wrote: > Add ipq5332 USB3 SS UNIPHY support. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- > 1 file changed, 114 insertions(+), 3 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: In file included from Documentation/devicetree/bindings/phy/qcom,uniphy.example.dts:45: ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:19: warning: "GCC_BLSP1_AHB_CLK" redefined 19 | #define GCC_BLSP1_AHB_CLK 10 | In file included from Documentation/devicetree/bindings/phy/qcom,uniphy.example.dts:18: ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:40: note: this is the location of the previous definition 40 | #define GCC_BLSP1_AHB_CLK 21 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:20: warning: "GCC_BLSP1_QUP1_I2C_APPS_CLK" redefined 20 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:41: note: this is the location of the previous definition 41 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:21: warning: "GCC_BLSP1_QUP1_SPI_APPS_CLK" redefined 21 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:42: note: this is the location of the previous definition 42 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:23: warning: "GCC_BLSP1_QUP2_I2C_APPS_CLK" redefined 23 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:43: note: this is the location of the previous definition 43 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:24: warning: "GCC_BLSP1_QUP2_SPI_APPS_CLK" redefined 24 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 15 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:44: note: this is the location of the previous definition 44 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:30: warning: "GCC_BLSP1_UART1_APPS_CLK" redefined 30 | #define GCC_BLSP1_UART1_APPS_CLK 21 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:45: note: this is the location of the previous definition 45 | #define GCC_BLSP1_UART1_APPS_CLK 26 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:32: warning: "GCC_BLSP1_UART2_APPS_CLK" redefined 32 | #define GCC_BLSP1_UART2_APPS_CLK 23 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:46: note: this is the location of the previous definition 46 | #define GCC_BLSP1_UART2_APPS_CLK 27 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:42: warning: "GCC_GP1_CLK" redefined 42 | #define GCC_GP1_CLK 33 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:48: note: this is the location of the previous definition 48 | #define GCC_GP1_CLK 29 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:44: warning: "GCC_GP2_CLK" redefined 44 | #define GCC_GP2_CLK 35 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:49: note: this is the location of the previous definition 49 | #define GCC_GP2_CLK 30 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:98: warning: "GCC_PRNG_AHB_CLK" redefined 98 | #define GCC_PRNG_AHB_CLK 89 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:62: note: this is the location of the previous definition 62 | #define GCC_PRNG_AHB_CLK 43 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:117: warning: "GCC_QPIC_AHB_CLK" redefined 117 | #define GCC_QPIC_AHB_CLK 108 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:63: note: this is the location of the previous definition 63 | #define GCC_QPIC_AHB_CLK 44 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:118: warning: "GCC_QPIC_CLK" redefined 118 | #define GCC_QPIC_CLK 109 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:64: note: this is the location of the previous definition 64 | #define GCC_QPIC_CLK 45 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:122: warning: "GCC_SDCC1_AHB_CLK" redefined 122 | #define GCC_SDCC1_AHB_CLK 113 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:65: note: this is the location of the previous definition 65 | #define GCC_SDCC1_AHB_CLK 46 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:123: warning: "GCC_SDCC1_APPS_CLK" redefined 123 | #define GCC_SDCC1_APPS_CLK 114 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:66: note: this is the location of the previous definition 66 | #define GCC_SDCC1_APPS_CLK 47 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:191: warning: "GCC_BLSP1_BCR" redefined 191 | #define GCC_BLSP1_BCR 8 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:126: note: this is the location of the previous definition 126 | #define GCC_BLSP1_BCR 30 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:192: warning: "GCC_BLSP1_QUP1_BCR" redefined 192 | #define GCC_BLSP1_QUP1_BCR 9 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:127: note: this is the location of the previous definition 127 | #define GCC_BLSP1_QUP1_BCR 31 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:195: warning: "GCC_BLSP1_QUP2_BCR" redefined 195 | #define GCC_BLSP1_QUP2_BCR 12 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:129: note: this is the location of the previous definition 129 | #define GCC_BLSP1_QUP2_BCR 33 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:203: warning: "GCC_BLSP1_UART1_BCR" redefined 203 | #define GCC_BLSP1_UART1_BCR 20 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:128: note: this is the location of the previous definition 128 | #define GCC_BLSP1_UART1_BCR 32 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:205: warning: "GCC_BLSP1_UART2_BCR" redefined 205 | #define GCC_BLSP1_UART2_BCR 22 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:130: note: this is the location of the previous definition 130 | #define GCC_BLSP1_UART2_BCR 34 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:260: warning: "GCC_PCNOC_BCR" redefined 260 | #define GCC_PCNOC_BCR 77 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:148: note: this is the location of the previous definition 148 | #define GCC_PCNOC_BCR 52 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:263: warning: "GCC_PRNG_BCR" redefined 263 | #define GCC_PRNG_BCR 80 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:135: note: this is the location of the previous definition 135 | #define GCC_PRNG_BCR 39 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:274: warning: "GCC_QDSS_BCR" redefined 274 | #define GCC_QDSS_BCR 91 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:165: note: this is the location of the previous definition 165 | #define GCC_QDSS_BCR 69 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:290: warning: "GCC_QPIC_BCR" redefined 290 | #define GCC_QPIC_BCR 107 | ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-ipq4019.h:141: note: this is the location of the previous definition 141 | #define GCC_QPIC_BCR 45 | doc reference errors (make refcheckdocs): Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml MAINTAINERS: Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230829135818.2219438-5-quic_ipkumar@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > This patch adds ipq5332 USB SS UNIPHY support. First, please read to Documentation/process/submitting-patches.rst, then rewrite the commit message. Next, I tend to say that this driver doesn't have a lot in common with the ipq4019 driver you have modified. Please consider adding new driver for ipq5332, then we can see whether it makes sense to fold ipq4019 to use new infrastructure. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > drivers/phy/qualcomm/phy-qcom-uniphy.c | 37 ++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c > index eb71588f5417..91487e68bb6e 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c > @@ -26,6 +26,10 @@ > #include <linux/regulator/consumer.h> > #include <linux/reset.h> > > +#define PCIE_USB_COMBO_PHY_CFG_MISC1 0x214 > +#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2 0x7C4 > +#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2 0x7E8 > + > struct uniphy_init_tbl { > unsigned int offset; > unsigned int val; > @@ -37,6 +41,12 @@ struct uniphy_init_tbl { > .val = v, \ > } > > +static const struct uniphy_init_tbl ipq5332_usb_ssphy_init_tbl[] = { > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_AFE_2, 0x1076), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2, 0x3142), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_MISC1, 0x3), > +}; > + > struct uniphy_cfg { > const struct uniphy_init_tbl *init_seq; > int num_init_seq; > @@ -83,6 +93,32 @@ static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { > .reset_udelay = 10000, > }; > > +static const char * const ipq5332_usb_ssphy_clk_l[] = { > + "phy_ahb", "phy_cfg_ahb", "pipe", > +}; > + > +static const char * const ipq5332_usb_ssphy_reset_l[] = { > + "por_rst", > +}; > + > +static const char * const ipq5332_usb_ssphy_vreg_l[] = { > + "vdda-phy", > +}; > + > +static const struct uniphy_cfg ipq5332_usb_ssphy_cfg = { > + .init_seq = ipq5332_usb_ssphy_init_tbl, > + .num_init_seq = ARRAY_SIZE(ipq5332_usb_ssphy_init_tbl), > + .clk_list = ipq5332_usb_ssphy_clk_l, > + .num_clks = ARRAY_SIZE(ipq5332_usb_ssphy_clk_l), > + .reset_list = ipq5332_usb_ssphy_reset_l, > + .num_resets = ARRAY_SIZE(ipq5332_usb_ssphy_reset_l), > + .vreg_list = ipq5332_usb_ssphy_vreg_l, > + .num_vregs = ARRAY_SIZE(ipq5332_usb_ssphy_vreg_l), > + .pipe_clk_rate = 250000000, > + .reset_udelay = 1, > + .autoload_udelay = 35, > +}; > + > static int phy_mux_sel(struct phy *phy) > { > struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > @@ -396,6 +432,7 @@ static int qcom_uniphy_probe(struct platform_device *pdev) > static const struct of_device_id qcom_uniphy_of_match[] = { > { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, > { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, > + { .compatible = "qcom,ipq5332-usb-ssphy", .data = &ipq5332_usb_ssphy_cfg}, > { }, > }; > MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); > -- > 2.34.1
On Tue, Aug 29, 2023 at 07:28:13PM +0530, Praveenkumar I wrote: > Add ipq5332 USB3 SS UNIPHY support. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- > 1 file changed, 114 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > index cbe2cc820009..17ba661b3d9b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > @@ -19,21 +19,53 @@ properties: > enum: > - qcom,usb-ss-ipq4019-phy > - qcom,usb-hs-ipq4019-phy > + - qcom,ipq5332-usb-ssphy > > reg: > maxItems: 1 > > + reg-names: > + items: > + - const: phy_base > + > + clocks: > + maxItems: 3 > + > + clock-names: > + maxItems: 3 > + > + "#clock-cells": > + const: 0 > + > resets: > + minItems: 1 > maxItems: 2 > > reset-names: > - items: > - - const: por_rst > - - const: srif_rst No need to remove this and duplicate the names multiple times. Just add 'minItems: 1' here and then the if/then schemas only need either minItems or maxItems. > + minItems: 1 > + maxItems: 2 > + > + clock-output-names: > + maxItems: 1 > > "#phy-cells": > const: 0 > > + qcom,phy-mux-sel: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + PHY Mux Selection for used to select which interface is going to use the > + combo PHY. > + items: > + - items: > + - description: phandle to TCSR syscon region > + - description: offset to the PHY Mux selection register > + - description: value to write on the PHY Mux selection register > + > + vdd-supply: > + description: > + Phandle to 5V regulator supply to PHY digital circuit. > + > required: > - compatible > - reg > @@ -41,6 +73,68 @@ required: > - reset-names > - "#phy-cells" > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,ipq5332-usb-ssphy > + then: > + properties: > + clocks: > + maxItems: 3 > + clock-names: > + items: > + - const: pipe > + - const: phy_cfg_ahb > + - const: phy_ahb How do the other variants work without any clocks? Magic? Define the names in the top level and then just set the number of items or disallow the property in the if/then schemas. > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: por_rst > + > + vdda-supply: > + description: > + Phandle to 5V regulator supply to PHY digital circuit. > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,usb-ss-ipq4019-phy > + then: > + properties: > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: por_rst > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,usb-hs-ipq4019-phy > + then: > + properties: > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: por_rst > + - const: srif_rst > + > additionalProperties: false > > examples: > @@ -55,3 +149,20 @@ examples: > <&gcc USB2_HSPHY_S_ARES>; > reset-names = "por_rst", "srif_rst"; > }; > + > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + > + ssuniphy@4b0000 { > + #phy-cells = <0>; > + #clock-cells = <0>; > + compatible = "qcom,ipq5332-usb-ssphy"; > + reg = <0x4b0000 0x800>; > + clocks = <&gcc GCC_USB0_PIPE_CLK>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; > + clock-names = "pipe", "phy_cfg_ahb", "phy_ahb"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>; > + reset-names = "por_rst"; > + }; > -- > 2.34.1 >
On 29/08/2023 15:58, Praveenkumar I wrote: > Add ipq5332 USB3 SS UNIPHY support. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- > 1 file changed, 114 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > index cbe2cc820009..17ba661b3d9b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > @@ -19,21 +19,53 @@ properties: > enum: > - qcom,usb-ss-ipq4019-phy > - qcom,usb-hs-ipq4019-phy > + - qcom,ipq5332-usb-ssphy > > reg: > maxItems: 1 > > + reg-names: > + items: > + - const: phy_base Why do you need it? > + > + clocks: > + maxItems: 3 > + > + clock-names: > + maxItems: 3 > + > + "#clock-cells": > + const: 0 > + ... > examples: > @@ -55,3 +149,20 @@ examples: > <&gcc USB2_HSPHY_S_ARES>; > reset-names = "por_rst", "srif_rst"; > }; > + > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + > + ssuniphy@4b0000 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > Enable UNIPHY driver for IPQ5322. This we see from the diff. You *must* say *why*, not *what*. Samsung IPQ5322 or NXP IPQ5322? Which boards need it? > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > How does it depend? Obviously it is part of the series, but what is depending here? Best regards, Krzysztof
On 29/08/2023 16:35, Rob Herring wrote: > > On Tue, 29 Aug 2023 19:28:13 +0530, Praveenkumar I wrote: >> Add ipq5332 USB3 SS UNIPHY support. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- >> 1 file changed, 114 insertions(+), 3 deletions(-) >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > In file included from Documentation/devicetree/bindings/phy/qcom,uniphy.example.dts:45: > ./scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h:19: warning: "GCC_BLSP1_AHB_CLK" redefined > 19 | #define GCC_BLSP1_AHB_CLK 10 > | So the only patch which actually needed dependency information did not have it. All other patches have something, even defconfig (!). Confusing. Best regards, Krzysztof
On 8/29/2023 7:49 PM, Dmitry Baryshkov wrote: > On Tue, 29 Aug 2023 at 16:59, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to >> ipq4019 PHY. Hence renaming this dt-binding to uniphy dt-binding and >> can be used for other qualcomm SoCs which are having similar UNIPHY. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> .../phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} | 9 +++++++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> rename Documentation/devicetree/bindings/phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} (78%) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >> similarity index 78% >> rename from Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml >> rename to Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >> index 09c614952fea..cbe2cc820009 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >> @@ -1,13 +1,18 @@ >> # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> %YAML 1.2 >> --- >> -$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# >> +$id: http://devicetree.org/schemas/phy/qcom,uniphy.yaml# >> $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> -title: Qualcom IPQ40xx Dakota HS/SS USB PHY >> +title: Qualcomm UNIPHY > We know that UNIPHY was a common design / IP block used for APQ8064 > SATA and MSM8974 DSI and HDMI PHYs. Is this the same design, or was > the name reused by the Qualcomm for some other PHYs? > Several latest generations have USB QMP PHYs which are called 'uni-phy'. This PHY is build on top of QCA Uniphy 22ull. A combo PHY used between USB Gen3 / PCIe Gen3 controller. It is different from USB QMP PHYs. - Praveenkumar >> maintainers: >> - Robert Marko <robert.marko@sartura.hr> >> + - Praveenkumar I <quic_ipkumar@quicinc.com> >> + >> +description: >> + UNIPHY / COMBO PHY supports physical layer functionality for USB and PCIe on >> + Qualcomm chipsets. >> >> properties: >> compatible: >> -- >> 2.34.1 >> >
On 8/29/2023 10:37 PM, Krzysztof Kozlowski wrote: > On 29/08/2023 15:58, Praveenkumar I wrote: >> IPQ5332 has UNIPHY for USB and PCIe which is similar to the UNIPHY >> present in IPQ4019. Few extra settings like clock, reset delay, mux >> selection and voltage regulator are required for IPQ5332. Hence >> repurposed the IPQ4019 PHY driver for IPQ5332 UNIPHY. Few more Qualcomm >> SoCs are also having the UNIPHY which can use the same driver for both >> USB and PCIe PHY. >> >> Praveenkumar I (9): >> dt-bindings: phy: qcom,uniphy: Rename ipq4019 usb PHY to UNIPHY >> phy: qcom: uniphy: Rename ipq4019 USB phy driver to UNIPHY driver >> phy: qcom: uniphy: Update UNIPHY driver to be a common driver >> dt-bindings: phy: qcom,uniphy: Add ipq5332 USB3 SS UNIPHY >> dt-bindings: usb: dwc3: Update IPQ5332 compatible >> arm64: dts: qcom: ipq5332: Add USB3 related nodes >> arm64: dts: qcom: ipq5332: Enable USB SS UNIPHY > DTS does not go before drivers. DTS should be sent separately or as the > last patches. If you stuff it in the middle, means your patchset has > dependencies which it cannot have. Thus it is broken. Sorry, I ordered it wrongly. Will correct in the next patches. - Praveenkumar > > Best regards, > Krzysztof >
On Thu, 31 Aug 2023 at 14:54, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > > On 8/29/2023 7:49 PM, Dmitry Baryshkov wrote: > > On Tue, 29 Aug 2023 at 16:59, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > >> UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to > >> ipq4019 PHY. Hence renaming this dt-binding to uniphy dt-binding and > >> can be used for other qualcomm SoCs which are having similar UNIPHY. > >> > >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > >> --- > >> .../phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} | 9 +++++++-- > >> 1 file changed, 7 insertions(+), 2 deletions(-) > >> rename Documentation/devicetree/bindings/phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} (78%) > >> > >> diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >> similarity index 78% > >> rename from Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml > >> rename to Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >> index 09c614952fea..cbe2cc820009 100644 > >> --- a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml > >> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >> @@ -1,13 +1,18 @@ > >> # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >> %YAML 1.2 > >> --- > >> -$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# > >> +$id: http://devicetree.org/schemas/phy/qcom,uniphy.yaml# > >> $schema: http://devicetree.org/meta-schemas/core.yaml# > >> > >> -title: Qualcom IPQ40xx Dakota HS/SS USB PHY > >> +title: Qualcomm UNIPHY > > We know that UNIPHY was a common design / IP block used for APQ8064 > > SATA and MSM8974 DSI and HDMI PHYs. Is this the same design, or was > > the name reused by the Qualcomm for some other PHYs? > > Several latest generations have USB QMP PHYs which are called 'uni-phy'. > This PHY is build on top of QCA Uniphy 22ull. A combo PHY used between > USB Gen3 / PCIe Gen3 controller. > It is different from USB QMP PHYs. So we have now three different items called Qualcomm uniphy. Could you please add some distinctive name? > > - Praveenkumar > >> maintainers: > >> - Robert Marko <robert.marko@sartura.hr> > >> + - Praveenkumar I <quic_ipkumar@quicinc.com> > >> + > >> +description: > >> + UNIPHY / COMBO PHY supports physical layer functionality for USB and PCIe on > >> + Qualcomm chipsets. > >> > >> properties: > >> compatible: > >> -- > >> 2.34.1 > >> > >
On Thu, 31 Aug 2023 at 15:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > > On 8/31/2023 5:47 PM, Dmitry Baryshkov wrote: > > On Thu, 31 Aug 2023 at 14:54, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > >> > >> On 8/29/2023 7:49 PM, Dmitry Baryshkov wrote: > >>> On Tue, 29 Aug 2023 at 16:59, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > >>>> UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to > >>>> ipq4019 PHY. Hence renaming this dt-binding to uniphy dt-binding and > >>>> can be used for other qualcomm SoCs which are having similar UNIPHY. > >>>> > >>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > >>>> --- > >>>> .../phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} | 9 +++++++-- > >>>> 1 file changed, 7 insertions(+), 2 deletions(-) > >>>> rename Documentation/devicetree/bindings/phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} (78%) > >>>> > >>>> diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >>>> similarity index 78% > >>>> rename from Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml > >>>> rename to Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >>>> index 09c614952fea..cbe2cc820009 100644 > >>>> --- a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml > >>>> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > >>>> @@ -1,13 +1,18 @@ > >>>> # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >>>> %YAML 1.2 > >>>> --- > >>>> -$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# > >>>> +$id: http://devicetree.org/schemas/phy/qcom,uniphy.yaml# > >>>> $schema: http://devicetree.org/meta-schemas/core.yaml# > >>>> > >>>> -title: Qualcom IPQ40xx Dakota HS/SS USB PHY > >>>> +title: Qualcomm UNIPHY > >>> We know that UNIPHY was a common design / IP block used for APQ8064 > >>> SATA and MSM8974 DSI and HDMI PHYs. Is this the same design, or was > >>> the name reused by the Qualcomm for some other PHYs? > >>> Several latest generations have USB QMP PHYs which are called 'uni-phy'. > >> This PHY is build on top of QCA Uniphy 22ull. A combo PHY used between > >> USB Gen3 / PCIe Gen3 controller. > >> It is different from USB QMP PHYs. > > So we have now three different items called Qualcomm uniphy. Could you > > please add some distinctive name? > There is one more target called IPQ5018 which is also having similar USB > PHY built on top of > Uniphy 28nm LP. That also can leverage this upcoming IPQ5332 USB PHY > driver. Considering that, > given a common name 'uniphy'. Just to verify, do we mean the same thing, when speaking about the 28nm LP UNIPHY? I was referencing the apq8064 SATA and msm8974 HDMI / DSI PHYs. See [1] and [2]. [1] https://patchwork.freedesktop.org/patch/544131/?series=118210&rev=2 [2] https://patchwork.freedesktop.org/patch/544125/?series=118210&rev=2 > > - Praveenkumar > > > >> - Praveenkumar > >>>> maintainers: > >>>> - Robert Marko <robert.marko@sartura.hr> > >>>> + - Praveenkumar I <quic_ipkumar@quicinc.com> > >>>> + > >>>> +description: > >>>> + UNIPHY / COMBO PHY supports physical layer functionality for USB and PCIe on > >>>> + Qualcomm chipsets. > >>>> > >>>> properties: > >>>> compatible: > >>>> -- > >>>> 2.34.1 > >>>> > > > >
On 8/31/2023 6:04 PM, Dmitry Baryshkov wrote: > On Thu, 31 Aug 2023 at 15:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> >> On 8/31/2023 5:47 PM, Dmitry Baryshkov wrote: >>> On Thu, 31 Aug 2023 at 14:54, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >>>> On 8/29/2023 7:49 PM, Dmitry Baryshkov wrote: >>>>> On Tue, 29 Aug 2023 at 16:59, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >>>>>> UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to >>>>>> ipq4019 PHY. Hence renaming this dt-binding to uniphy dt-binding and >>>>>> can be used for other qualcomm SoCs which are having similar UNIPHY. >>>>>> >>>>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >>>>>> --- >>>>>> .../phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} | 9 +++++++-- >>>>>> 1 file changed, 7 insertions(+), 2 deletions(-) >>>>>> rename Documentation/devicetree/bindings/phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} (78%) >>>>>> >>>>>> diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >>>>>> similarity index 78% >>>>>> rename from Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml >>>>>> rename to Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >>>>>> index 09c614952fea..cbe2cc820009 100644 >>>>>> --- a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml >>>>>> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml >>>>>> @@ -1,13 +1,18 @@ >>>>>> # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>>>>> %YAML 1.2 >>>>>> --- >>>>>> -$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# >>>>>> +$id: http://devicetree.org/schemas/phy/qcom,uniphy.yaml# >>>>>> $schema: http://devicetree.org/meta-schemas/core.yaml# >>>>>> >>>>>> -title: Qualcom IPQ40xx Dakota HS/SS USB PHY >>>>>> +title: Qualcomm UNIPHY >>>>> We know that UNIPHY was a common design / IP block used for APQ8064 >>>>> SATA and MSM8974 DSI and HDMI PHYs. Is this the same design, or was >>>>> the name reused by the Qualcomm for some other PHYs? >>>>> Several latest generations have USB QMP PHYs which are called 'uni-phy'. >>>> This PHY is build on top of QCA Uniphy 22ull. A combo PHY used between >>>> USB Gen3 / PCIe Gen3 controller. >>>> It is different from USB QMP PHYs. >>> So we have now three different items called Qualcomm uniphy. Could you >>> please add some distinctive name? >> There is one more target called IPQ5018 which is also having similar USB >> PHY built on top of >> Uniphy 28nm LP. That also can leverage this upcoming IPQ5332 USB PHY >> driver. Considering that, >> given a common name 'uniphy'. > Just to verify, do we mean the same thing, when speaking about the > 28nm LP UNIPHY? > I was referencing the apq8064 SATA and msm8974 HDMI / DSI PHYs. See [1] and [2]. > > [1] https://patchwork.freedesktop.org/patch/544131/?series=118210&rev=2 > [2] https://patchwork.freedesktop.org/patch/544125/?series=118210&rev=2 No, this seems different from the PHY used on IPQ5018 / IPQ5332. PHY in QualcommIPQ targets requires minimal SW configuration for the bring up. >> - Praveenkumar >>>> - Praveenkumar >>>>>> maintainers: >>>>>> - Robert Marko <robert.marko@sartura.hr> >>>>>> + - Praveenkumar I <quic_ipkumar@quicinc.com> >>>>>> + >>>>>> +description: >>>>>> + UNIPHY / COMBO PHY supports physical layer functionality for USB and PCIe on >>>>>> + Qualcomm chipsets. >>>>>> >>>>>> properties: >>>>>> compatible: >>>>>> -- >>>>>> 2.34.1 >>>>>> >>> > >