| Message ID | 20230825093219.2685912-16-yoshihiro.shimoda.uh@renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: rcar-gen4: Add R-Car Gen4 PCIe support | expand |
Hi Shimoda-san, On Fri, Aug 25, 2023 at 3:57 PM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) > PCIe endpoint module. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > Acked-by: Manivannan Sadhasivam <mani@kernel.org> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > @@ -0,0 +1,106 @@ > + resets: > + maxItems: 1 Missing reset-names, cfr. Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - resets > + - power-domains > + - clocks > + - clock-names Missing reset-names. > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/r8a779f0-sysc.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie0_ep: pcie-ep@e65d0000 { > + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; > + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x0800>, <0 0xe65d2800 0 0x0800> does not match your DTS patch https://lore.kernel.org/linux-renesas-soc/20230828041434.2747699-2-yoshihiro.shimoda.uh@renesas.com > + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, > + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; > + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space"; > + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; What about SPI 419, 420, 421? > + interrupt-names = "dma", "sft_ce", "app"; > + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; > + clock-names = "core", "ref"; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 624>; > + num-lanes = <2>; > + max-link-speed = <4>; > + max-functions = /bits/ 8 <2>; > + }; > + }; BTW, I think it would be good to make the order of the properties and in the example match between the host and endpoint bindings, to make the output of "diff Documentation/devicetree/bindings/pci/rcar-gen4-pci-{host,ep}.yaml" as small as possible. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml new file mode 100644 index 000000000000..4e6be856104c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Endpoint + +maintainers: + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +allOf: + - $ref: snps,dw-pcie-ep.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 + + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: addr_space + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: dma + - const: sft_ce + - const: app + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: ref + + max-functions: + maximum: 2 + + max-link-speed: + maximum: 4 + + num-lanes: + maximum: 4 + +required: + - compatible + - reg + - reg-names + - interrupts + - resets + - power-domains + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a779f0-sysc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x0800>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space"; + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + max-link-speed = <4>; + max-functions = /bits/ 8 <2>; + }; + };