| Message ID | 20230827203612.173562-1-tmaimon77@gmail.com |
|---|---|
| Headers | show |
| Series | pinctrl: nuvoton: add pinmux and GPIO driver for NPCM8XX | expand |
On 27/08/2023 22:36, Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX > pinmux and GPIO controller. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > + '^pin': > + $ref: pincfg-node.yaml# > + > + properties: > + pins: > + description: > + A list of pins to configure in certain ways, such as enabling > + debouncing What pin names are allowed? > + > + bias-disable: true > + > + bias-pull-up: true > + > + bias-pull-down: true > + > + input-enable: true > + > + output-low: true > + > + output-high: true > + > + drive-push-pull: true > + > + drive-open-drain: true > + > + input-debounce: > + description: > + Debouncing periods in microseconds, one period per interrupt > + bank found in the controller > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 > + > + slew-rate: > + description: | > + 0: Low rate > + 1: High rate > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1] > + > + drive-strength: > + enum: [ 0, 1, 2, 4, 8, 12 ] > + > + additionalProperties: false > + > +allOf: > + - $ref: pinctrl.yaml# > + > +required: > + - compatible > + - ranges > + - '#address-cells' > + - '#size-cells' > + - nuvoton,sysgcr > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/gpio/gpio.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pinctrl: pinctrl@f0800260 { Nothing improved here. Test your DTS. This is being reported - I checked. > + compatible = "nuvoton,npcm845-pinctrl"; > + ranges = <0x0 0x0 0xf0010000 0x8000>; > + #address-cells = <1>; > + #size-cells = <1>; > + nuvoton,sysgcr = <&gcr>; > + > + gpio0: gpio@0 { > + gpio-controller; > + #gpio-cells = <2>; > + reg = <0x0 0xB0>; Keep lowercase hex. Best regards, Krzysztof
On 28/08/2023 12:26, Tomer Maimon wrote: > Hi Krzysztof, > > Thanks for your comments > > On Mon, 28 Aug 2023 at 10:10, Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> On 27/08/2023 22:36, Tomer Maimon wrote: >>> Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX >>> pinmux and GPIO controller. >>> >>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> >>> Reviewed-by: Rob Herring <robh@kernel.org> >>> --- >> >> >>> + '^pin': >>> + $ref: pincfg-node.yaml# >>> + >>> + properties: >>> + pins: >>> + description: >>> + A list of pins to configure in certain ways, such as enabling >>> + debouncing >> >> What pin names are allowed? > Do you mean to describe all the allowed pin items? > for example: > items: > pattern: > 'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' > or > items: > pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$' > > is good enough? Something like this. Whichever is correct. >> >>> + >>> + bias-disable: true >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + - | >>> + #include <dt-bindings/interrupt-controller/arm-gic.h> >>> + #include <dt-bindings/gpio/gpio.h> >>> + >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + pinctrl: pinctrl@f0800260 { >> >> Nothing improved here. Test your DTS. This is being reported - I checked. > what do you suggest since the pinctrl doesn't have a reg parameter, > maybe pinctrl: pinctrl@0? It has ranges, so yes @0 looks correct here. Which leds to second question - how pinctrl could have @0? It's already taken by SoC! So your DTS here - unit address and ranges - are clearly wrong. > BTW, I have run both dt_binding_check and W=1 dtbs_check, and didn't > see an issue related to the pinctrl: pinctrl@f0800260, do I need to > add another flag to see the issue? Did you read my message last time? I said - it's about DTS, not the binding. Best regards, Krzysztof
Hi Krzysztof, Thanks for your clarifications On Mon, 28 Aug 2023 at 13:39, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 28/08/2023 12:36, Krzysztof Kozlowski wrote: > > On 28/08/2023 12:26, Tomer Maimon wrote: > >> Hi Krzysztof, > >> > >> Thanks for your comments > >> > >> On Mon, 28 Aug 2023 at 10:10, Krzysztof Kozlowski > >> <krzysztof.kozlowski@linaro.org> wrote: > >>> > >>> On 27/08/2023 22:36, Tomer Maimon wrote: > >>>> Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX > >>>> pinmux and GPIO controller. > >>>> > >>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > >>>> Reviewed-by: Rob Herring <robh@kernel.org> > >>>> --- > >>> > >>> > >>>> + '^pin': > >>>> + $ref: pincfg-node.yaml# > >>>> + > >>>> + properties: > >>>> + pins: > >>>> + description: > >>>> + A list of pins to configure in certain ways, such as enabling > >>>> + debouncing > >>> > >>> What pin names are allowed? > >> Do you mean to describe all the allowed pin items? > >> for example: > >> items: > >> pattern: > >> 'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' > >> or > >> items: > >> pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$' > >> > >> is good enough? > > > > Something like this. Whichever is correct. > > > >>> > >>>> + > >>>> + bias-disable: true > >>>> + > > > >>>> +additionalProperties: false > >>>> + > >>>> +examples: > >>>> + - | > >>>> + #include <dt-bindings/interrupt-controller/arm-gic.h> > >>>> + #include <dt-bindings/gpio/gpio.h> > >>>> + > >>>> + soc { > >>>> + #address-cells = <2>; > >>>> + #size-cells = <2>; > >>>> + > >>>> + pinctrl: pinctrl@f0800260 { > >>> > >>> Nothing improved here. Test your DTS. This is being reported - I checked. > >> what do you suggest since the pinctrl doesn't have a reg parameter, > >> maybe pinctrl: pinctrl@0? > > > > It has ranges, so yes @0 looks correct here. > > Wait, your address according to ranges is 0xf0010000, not 0x0, not > 0xf0800260... I will modify it to pinctrl: pinctrl@f0010000 > > > > Which leds to second > > question - how pinctrl could have @0? It's already taken by SoC! So your > > DTS here - unit address and ranges - are clearly wrong. > > > > > >> BTW, I have run both dt_binding_check and W=1 dtbs_check, and didn't > >> see an issue related to the pinctrl: pinctrl@f0800260, do I need to > >> add another flag to see the issue? > > > > Did you read my message last time? I said - it's about DTS, not the binding. yes, understood doesn't the dtbs_check check the DTS? > > Best regards, > Krzysztof > Best regards, Tomer
This patch set adds pinmux and GPIO controller for the Arbel NPCM8XX Baseboard Management Controller (BMC). Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the pin mux mapping difference the NPCM8XX GPIO supports adjust debounce period time. Arbel BMC NPCM8XX Pinmux functions accessible only for pin groups and pin configuration parameters available only for individual pins. Arbel BMC NPCM8XX has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM8XX pinctrl and GPIO driver were tested on NPCM845 evaluation board. Addressed comments from: - Rob Herring: https://lore.kernel.org/lkml/20230821170941.GA1915730-robh@kernel.org/ - Krzysztof Kozlowski: https://lore.kernel.org/lkml/ddaa0a85-111b-5289-b8eb-afae5e5ab1df@linaro.org/ Changes since version 5: - Pin controller dt-binding - Modify gpio unit-address. - Remove blank line at EOF. Changes since version 4: - Pin controller driver - Modify DS definition. - Pin controller dt-binding - Modify -mux pattern. - Remove tabs. Changes since version 3: - Pin controller driver - Remove unused line in Kconfig. - Add GPIO 183-189 GPIO support. - Add SPI1 CS pins. - Modify SMB23b pin list. - Remove unused module pins. - Fix PIN-CONFIG_OUTPUT setting. - Pin controller dt-binding - Modify pin and function items. - Use consistent quotes. - drop unneseccary quote. - pincrtl node name modify to pinctrl@f0800260 since the pin controller handling was done in 0xf0800260 offset. Changes since version 2: - Pin controller driver - Modify kernel configuration. - Adding and removing include files. - Using the same register format size. - Reducing lines by command combination. - Remove unnecessary parentheses use. - Use GENMASK and BIT macros. - Using traditional patterns. - Pin controller dt-binding - Modify GPIO description. - pintcrtl node name, Sorry, I know we have a long discussion about it. Still, I think the best header pinctrl node name is pinctrl@f0800000. because the pin mux is handled through the GCR. BTW, same pinctrl header name is used in the NPCM7XX pinctrl version. https://elixir.bootlin.com/linux/v6.0-rc6/source/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi#L560 Changes since version 1: - Pin controller driver - Remove unnecessary debug prints and comments. - Use fwnode functions. - Remove Redundant 'else'. - Use switch case instead of else if. - Use GENMASK and BIT macros. - Use dev_err_probe in probe error. - Use callback GPIO range. - Add GCR phandle property. - Parameter order in reversed xmas - Pin controller dt-binding - Modify name from pin to mux. - Add phandle property. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver .../pinctrl/nuvoton,npcm845-pinctrl.yaml | 214 ++ drivers/pinctrl/nuvoton/Kconfig | 14 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2491 +++++++++++++++++ 4 files changed, 2720 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c