mbox series

[v4,0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

Message ID 20230827032803.934819-1-dmitry.baryshkov@linaro.org
Headers show
Series cpufreq: qcom-nvmem: support apq8064 cpufreq scaling | expand

Message

Dmitry Baryshkov Aug. 27, 2023, 3:27 a.m. UTC 
This is a split of APQ8064 cpufreq series, as requested by Viresh. This
series includes only opp and cpufreq parts, with the DT and soc parts
being split to a separate patchset.

Each core has independent power and frequency control. Additionally the
L2 cache is scaled to follow the CPU frequencies (failure to do so
results in strange semi-random crashes).

Core voltage is controlled through the SAW2 devices, one for each core.
The L2 has two regulators, vdd-mem and vdd-dig.

Dmitry Baryshkov (6):
  dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
  cpufreq: qcom-nvmem: create L2 cache device
  cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
  cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
  cpufreq: qcom-nvmem: provide separate configuration data for apq8064
  cpufreq: qcom-nvmem: enable core voltage scaling for MSM8960

 .../bindings/opp/opp-v2-kryo-cpu.yaml         | 12 ++-
 drivers/cpufreq/qcom-cpufreq-nvmem.c          | 80 +++++++++++++++++--
 2 files changed, 81 insertions(+), 11 deletions(-)

Comments

Konrad Dybcio Aug. 28, 2023, 9:43 a.m. UTC | #1 
On 27.08.2023 05:27, Dmitry Baryshkov wrote:
> This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> series includes only opp and cpufreq parts, with the DT and soc parts
> being split to a separate patchset.
> 
> Each core has independent power and frequency control. Additionally the
> L2 cache is scaled to follow the CPU frequencies (failure to do so
> results in strange semi-random crashes).
> 
> Core voltage is controlled through the SAW2 devices, one for each core.
> The L2 has two regulators, vdd-mem and vdd-dig.
> 
No changelog?

Konrad
Dmitry Baryshkov Aug. 28, 2023, 9:51 a.m. UTC | #2 
On Mon, 28 Aug 2023 at 12:43, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 27.08.2023 05:27, Dmitry Baryshkov wrote:
> > This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> > series includes only opp and cpufreq parts, with the DT and soc parts
> > being split to a separate patchset.
> >
> > Each core has independent power and frequency control. Additionally the
> > L2 cache is scaled to follow the CPU frequencies (failure to do so
> > results in strange semi-random crashes).
> >
> > Core voltage is controlled through the SAW2 devices, one for each core.
> > The L2 has two regulators, vdd-mem and vdd-dig.
> >
> No changelog?

Missed it while performing the split.

Changes since v3:
- Unrolled loops in krait_l2_config_regulators() (Konrad)
Konrad Dybcio Aug. 28, 2023, 11:07 a.m. UTC | #3 
On 27.08.2023 05:27, Dmitry Baryshkov wrote:
> Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
> APQ8064) also requires scaling of the L2 cache frequency. As the
> l2-cache device node is places under /cpus/ path, it is not created by
> default by the OF code. Create corresponding device here.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 84d7033e5efe..f4c196ba4432 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -22,6 +22,7 @@
>  #include <linux/module.h>
>  #include <linux/nvmem-consumer.h>
>  #include <linux/of.h>
> +#include <linux/of_platform.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_domain.h>
>  #include <linux/pm_opp.h>
> @@ -377,6 +378,7 @@ static int __init qcom_cpufreq_init(void)
>  {
>  	struct device_node *np = of_find_node_by_path("/");
>  	const struct of_device_id *match;
> +	unsigned int cpu;
>  	int ret;
>  
>  	if (!np)
> @@ -387,6 +389,25 @@ static int __init qcom_cpufreq_init(void)
>  	if (!match)
>  		return -ENODEV;
>  
> +	for_each_possible_cpu(cpu) {
> +		struct device *dev = get_cpu_device(cpu);
> +		struct device_node *cache;
> +		struct platform_device *pdev;
Aaaalmost reverse-Christmas-tree :D

> +
> +		cache = of_find_next_cache_node(dev->of_node);
> +		if (!cache)
> +			continue;
> +
> +		if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) {
> +			pdev = of_platform_device_create(cache, NULL, NULL);
> +			if (IS_ERR(pdev))
> +				pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev);
The return value should be null-checked instead


> +			/* the error is not fatal */
"This error"?

Konrad