| Message ID | 20230810023548.412310-3-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement cortex-a710 | expand |
On Thu, 10 Aug 2023 at 03:37, Richard Henderson <richard.henderson@linaro.org> wrote: > > This value is only 4 bits wide. True. Any particular reason to change the type, though? > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 8/10/23 07:09, Peter Maydell wrote: > On Thu, 10 Aug 2023 at 03:37, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> This value is only 4 bits wide. > > True. Any particular reason to change the type, though? To save space. r~ > >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/cpu.h | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > thanks > -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda6..7fedbb34ba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,8 @@ struct ArchCPU { bool prop_lpa2; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ - uint32_t dcz_blocksize; + uint8_t dcz_blocksize; + uint64_t rvbar_prop; /* Property/input signals. */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
This value is only 4 bits wide. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)