| Message ID | 20230807150618.101357-1-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS | expand |
On 8/7/23 08:06, Peter Maydell wrote: > The architecture requires (R_TYTWB) that an attempt to return from EL3 > when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This > enforces that the CPU can't ever be executing below EL3 with the > NSE,NS bits indicating an invalid security state.) > > We were missing this check; add it. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/tcg/helper-a64.c | 9 +++++++++ > 1 file changed, 9 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 1c9370f07bd..0cf56f6dc44 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -780,6 +780,15 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) spsr &= ~PSTATE_SS; } + /* + * FEAT_RME forbids return from EL3 with an invalid security state. + * We don't need an explicit check for FEAT_RME here because we enforce + * in scr_write() that you can't set the NSE bit without it. + */ + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { + goto illegal_return; + } + new_el = el_from_spsr(spsr); if (new_el == -1) { goto illegal_return;
The architecture requires (R_TYTWB) that an attempt to return from EL3 when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This enforces that the CPU can't ever be executing below EL3 with the NSE,NS bits indicating an invalid security state.) We were missing this check; add it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/helper-a64.c | 9 +++++++++ 1 file changed, 9 insertions(+)