| Message ID | 20230803-amlogic-v6-4-upstream-dsi-ccf-vim3-v7-0-762219fc5b28@linaro.org |
|---|---|
| Headers | show |
| Series | drm/meson: add support for MIPI DSI Display | expand |
On Thu 03 Aug 2023 at 14:03, Neil Armstrong <neil.armstrong@linaro.org> wrote: > The VCLK and VCLK_DIV clocks have supplementary bits. > > The VCLK has a "SOFT RESET" bit to toggle after the whole > VCLK sub-tree rate has been set, this is implemented in > the gate enable callback. > > The VCLK_DIV clocks as enable and reset bits used to disable > and reset the divider, associated with CLK_SET_RATE_GATE it ensures > the rate is set while the divider is disabled and in reset mode. > > The VCLK_DIV enable bit isn't implemented as a gate since it's part > of the divider logic and vendor does this exact sequence to ensure > the divider is correctly set. Unless there is reason, I'd prefer if this driver was using 'struct parm', like the rest of amlogic custom clock drivers, for consistency. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/clk/meson/Kconfig | 5 ++ > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/vclk.c | 146 +++++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/meson/vclk.h | 68 +++++++++++++++++++++ > 4 files changed, 220 insertions(+) > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index 135da8f2d0b1..83f629515e96 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV > tristate > select COMMON_CLK_MESON_REGMAP > > +config COMMON_CLK_MESON_VCLK > + tristate > + select COMMON_CLK_MESON_REGMAP > + > config COMMON_CLK_MESON_CLKC_UTILS > tristate > > @@ -140,6 +144,7 @@ config COMMON_CLK_G12A > select COMMON_CLK_MESON_EE_CLKC > select COMMON_CLK_MESON_CPU_DYNDIV > select COMMON_CLK_MESON_VID_PLL_DIV > + select COMMON_CLK_MESON_VCLK > select MFD_SYSCON > help > Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index cd961cc4f4db..6efeb8c7bd2a 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o > obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o > obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o > obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o > +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o > > # Amlogic Clock controllers > > diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c > new file mode 100644 > index 000000000000..0df84403b17f > --- /dev/null > +++ b/drivers/clk/meson/vclk.c > @@ -0,0 +1,146 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> > + */ > + > +#include <linux/module.h> > +#include "vclk.h" > + > +/* The VCLK gate has a supplementary reset bit to pulse after ungating */ > + > +static int clk_regmap_vclk_enable(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); > + > + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); > + > + /* Do a reset pulse */ > + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); > + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); > + > + return 0; > +} > + > +static void clk_regmap_vclk_disable(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); > + > + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); > +} > + > +static int clk_regmap_vclk_is_enabled(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); > + unsigned int val; > + > + regmap_read(clk->map, vclk->offset, &val); > + > + return val & BIT(vclk->enable_bit_idx) ? 1 : 0; > +} > + > +const struct clk_ops clk_regmap_vclk_ops = { > + .enable = clk_regmap_vclk_enable, > + .disable = clk_regmap_vclk_disable, > + .is_enabled = clk_regmap_vclk_is_enabled, > +}; > +EXPORT_SYMBOL_GPL(clk_regmap_vclk_ops); > + > +/* The VCLK Divider has supplementary reset & enable bits */ > + > +static unsigned long clk_regmap_vclk_div_recalc_rate(struct clk_hw *hw, > + unsigned long prate) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + unsigned int val; > + int ret; > + > + ret = regmap_read(clk->map, vclk->offset, &val); > + if (ret) > + /* Gives a hint that something is wrong */ > + return 0; > + > + val >>= vclk->shift; > + val &= clk_div_mask(vclk->width); > + > + return divider_recalc_rate(hw, prate, val, vclk->table, vclk->flags, > + vclk->width); > +} > + > +static int clk_regmap_vclk_div_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + > + return divider_determine_rate(hw, req, vclk->table, vclk->width, > + vclk->flags); > +} > + > +static int clk_regmap_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + unsigned int val; > + int ret; > + > + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->width, > + vclk->flags); > + if (ret < 0) > + return ret; > + > + val = (unsigned int)ret << vclk->shift; > + return regmap_update_bits(clk->map, vclk->offset, > + clk_div_mask(vclk->width) << vclk->shift, val); > +}; > + > +static int clk_regmap_vclk_div_enable(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + > + /* Unreset the divider when ungating */ > + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); > + > + return regmap_set_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); > +} > + > +static void clk_regmap_vclk_div_disable(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + > + /* Reset the divider when gating */ > + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); > + > + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); > +} > + > +static int clk_regmap_vclk_div_is_enabled(struct clk_hw *hw) > +{ > + struct clk_regmap *clk = to_clk_regmap(hw); > + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); > + unsigned int val; > + > + regmap_read(clk->map, vclk->offset, &val); > + > + return val & BIT(vclk->enable_bit_idx) ? 1 : 0; > +} > + > +const struct clk_ops clk_regmap_vclk_div_ops = { > + .recalc_rate = clk_regmap_vclk_div_recalc_rate, > + .determine_rate = clk_regmap_vclk_div_determine_rate, > + .set_rate = clk_regmap_vclk_div_set_rate, > + .enable = clk_regmap_vclk_div_enable, > + .disable = clk_regmap_vclk_div_disable, > + .is_enabled = clk_regmap_vclk_div_is_enabled, > +}; > +EXPORT_SYMBOL_GPL(clk_regmap_vclk_div_ops); > + > +MODULE_DESCRIPTION("Amlogic vclk clock driver"); > +MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>"); > +MODULE_LICENSE("GPL v2"); > diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h > new file mode 100644 > index 000000000000..90786552a7f3 > --- /dev/null > +++ b/drivers/clk/meson/vclk.h > @@ -0,0 +1,68 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> > + */ > + > +#ifndef __VCLK_H > +#define __VCLK_H > + > +#include "clk-regmap.h" > + > +/** > + * struct clk_regmap_vclk_data - vclk regmap backed specific data > + * > + * @offset: offset of the register controlling gate > + * @enable_bit_idx: single bit controlling vclk enable > + * @reset_bit_idx: single bit controlling vclk reset > + * @flags: hardware-specific flags > + * > + * Flags: > + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored > + */ > +struct clk_regmap_vclk_data { > + unsigned int offset; > + u8 enable_bit_idx; > + u8 reset_bit_idx; > + u8 flags; > +}; > + > +static inline struct clk_regmap_vclk_data * > +clk_get_regmap_vclk_data(struct clk_regmap *clk) > +{ > + return (struct clk_regmap_vclk_data *)clk->data; > +} > + > +extern const struct clk_ops clk_regmap_vclk_ops; > + > +/** > + * struct clk_regmap_vclk_div_data - vclk_div regmap back specific data > + * > + * @offset: offset of the register controlling the divider > + * @shift: shift to the divider bit field > + * @width: width of the divider bit field > + * @enable_bit_idx: single bit controlling vclk divider enable > + * @reset_bit_idx: single bit controlling vclk divider reset > + * @table: array of value/divider pairs, last entry should have div = 0 > + * > + * Flags: > + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored > + */ > +struct clk_regmap_vclk_div_data { > + unsigned int offset; > + u8 shift; > + u8 width; > + u8 enable_bit_idx; > + u8 reset_bit_idx; > + const struct clk_div_table *table; > + u8 flags; > +}; > + > +static inline struct clk_regmap_vclk_div_data * > +clk_get_regmap_vclk_div_data(struct clk_regmap *clk) > +{ > + return (struct clk_regmap_vclk_div_data *)clk->data; > +} > + > +extern const struct clk_ops clk_regmap_vclk_div_ops; > + > +#endif /* __VCLK_H */
On 04/08/2023 09:33, Jerome Brunet wrote: > > On Thu 03 Aug 2023 at 14:03, Neil Armstrong <neil.armstrong@linaro.org> wrote: > >> The VCLK and VCLK_DIV clocks have supplementary bits. >> >> The VCLK has a "SOFT RESET" bit to toggle after the whole >> VCLK sub-tree rate has been set, this is implemented in >> the gate enable callback. >> >> The VCLK_DIV clocks as enable and reset bits used to disable >> and reset the divider, associated with CLK_SET_RATE_GATE it ensures >> the rate is set while the divider is disabled and in reset mode. >> >> The VCLK_DIV enable bit isn't implemented as a gate since it's part >> of the divider logic and vendor does this exact sequence to ensure >> the divider is correctly set. > > Unless there is reason, I'd prefer if this driver was using 'struct > parm', like the rest of amlogic custom clock drivers, for consistency. Ack thx, Neil > >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/clk/meson/Kconfig | 5 ++ >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/vclk.c | 146 +++++++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/meson/vclk.h | 68 +++++++++++++++++++++ >> 4 files changed, 220 insertions(+) >> >> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig >> index 135da8f2d0b1..83f629515e96 100644 >> --- a/drivers/clk/meson/Kconfig >> +++ b/drivers/clk/meson/Kconfig >> @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV >> tristate >> select COMMON_CLK_MESON_REGMAP >> >> +config COMMON_CLK_MESON_VCLK >> + tristate >> + select COMMON_CLK_MESON_REGMAP >> + >> config COMMON_CLK_MESON_CLKC_UTILS >> tristate >> >> @@ -140,6 +144,7 @@ config COMMON_CLK_G12A >> select COMMON_CLK_MESON_EE_CLKC >> select COMMON_CLK_MESON_CPU_DYNDIV >> select COMMON_CLK_MESON_VID_PLL_DIV >> + select COMMON_CLK_MESON_VCLK >> select MFD_SYSCON >> help >> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index cd961cc4f4db..6efeb8c7bd2a 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o >> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o >> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o >> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o >> +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o >> >> # Amlogic Clock controllers >> >> diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c >> new file mode 100644 >> index 000000000000..0df84403b17f >> --- /dev/null >> +++ b/drivers/clk/meson/vclk.c >> @@ -0,0 +1,146 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> >> + */ >> + >> +#include <linux/module.h> >> +#include "vclk.h" >> + >> +/* The VCLK gate has a supplementary reset bit to pulse after ungating */ >> + >> +static int clk_regmap_vclk_enable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); >> + >> + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); >> + >> + /* Do a reset pulse */ >> + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); >> + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); >> + >> + return 0; >> +} >> + >> +static void clk_regmap_vclk_disable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); >> + >> + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); >> +} >> + >> +static int clk_regmap_vclk_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_data *vclk = clk_get_regmap_vclk_data(clk); >> + unsigned int val; >> + >> + regmap_read(clk->map, vclk->offset, &val); >> + >> + return val & BIT(vclk->enable_bit_idx) ? 1 : 0; >> +} >> + >> +const struct clk_ops clk_regmap_vclk_ops = { >> + .enable = clk_regmap_vclk_enable, >> + .disable = clk_regmap_vclk_disable, >> + .is_enabled = clk_regmap_vclk_is_enabled, >> +}; >> +EXPORT_SYMBOL_GPL(clk_regmap_vclk_ops); >> + >> +/* The VCLK Divider has supplementary reset & enable bits */ >> + >> +static unsigned long clk_regmap_vclk_div_recalc_rate(struct clk_hw *hw, >> + unsigned long prate) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + unsigned int val; >> + int ret; >> + >> + ret = regmap_read(clk->map, vclk->offset, &val); >> + if (ret) >> + /* Gives a hint that something is wrong */ >> + return 0; >> + >> + val >>= vclk->shift; >> + val &= clk_div_mask(vclk->width); >> + >> + return divider_recalc_rate(hw, prate, val, vclk->table, vclk->flags, >> + vclk->width); >> +} >> + >> +static int clk_regmap_vclk_div_determine_rate(struct clk_hw *hw, >> + struct clk_rate_request *req) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + >> + return divider_determine_rate(hw, req, vclk->table, vclk->width, >> + vclk->flags); >> +} >> + >> +static int clk_regmap_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate, >> + unsigned long parent_rate) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + unsigned int val; >> + int ret; >> + >> + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->width, >> + vclk->flags); >> + if (ret < 0) >> + return ret; >> + >> + val = (unsigned int)ret << vclk->shift; >> + return regmap_update_bits(clk->map, vclk->offset, >> + clk_div_mask(vclk->width) << vclk->shift, val); >> +}; >> + >> +static int clk_regmap_vclk_div_enable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + >> + /* Unreset the divider when ungating */ >> + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); >> + >> + return regmap_set_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); >> +} >> + >> +static void clk_regmap_vclk_div_disable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + >> + /* Reset the divider when gating */ >> + regmap_clear_bits(clk->map, vclk->offset, BIT(vclk->enable_bit_idx)); >> + >> + regmap_set_bits(clk->map, vclk->offset, BIT(vclk->reset_bit_idx)); >> +} >> + >> +static int clk_regmap_vclk_div_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct clk_regmap_vclk_div_data *vclk = clk_get_regmap_vclk_div_data(clk); >> + unsigned int val; >> + >> + regmap_read(clk->map, vclk->offset, &val); >> + >> + return val & BIT(vclk->enable_bit_idx) ? 1 : 0; >> +} >> + >> +const struct clk_ops clk_regmap_vclk_div_ops = { >> + .recalc_rate = clk_regmap_vclk_div_recalc_rate, >> + .determine_rate = clk_regmap_vclk_div_determine_rate, >> + .set_rate = clk_regmap_vclk_div_set_rate, >> + .enable = clk_regmap_vclk_div_enable, >> + .disable = clk_regmap_vclk_div_disable, >> + .is_enabled = clk_regmap_vclk_div_is_enabled, >> +}; >> +EXPORT_SYMBOL_GPL(clk_regmap_vclk_div_ops); >> + >> +MODULE_DESCRIPTION("Amlogic vclk clock driver"); >> +MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>"); >> +MODULE_LICENSE("GPL v2"); >> diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h >> new file mode 100644 >> index 000000000000..90786552a7f3 >> --- /dev/null >> +++ b/drivers/clk/meson/vclk.h >> @@ -0,0 +1,68 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> >> + */ >> + >> +#ifndef __VCLK_H >> +#define __VCLK_H >> + >> +#include "clk-regmap.h" >> + >> +/** >> + * struct clk_regmap_vclk_data - vclk regmap backed specific data >> + * >> + * @offset: offset of the register controlling gate >> + * @enable_bit_idx: single bit controlling vclk enable >> + * @reset_bit_idx: single bit controlling vclk reset >> + * @flags: hardware-specific flags >> + * >> + * Flags: >> + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored >> + */ >> +struct clk_regmap_vclk_data { >> + unsigned int offset; >> + u8 enable_bit_idx; >> + u8 reset_bit_idx; >> + u8 flags; >> +}; >> + >> +static inline struct clk_regmap_vclk_data * >> +clk_get_regmap_vclk_data(struct clk_regmap *clk) >> +{ >> + return (struct clk_regmap_vclk_data *)clk->data; >> +} >> + >> +extern const struct clk_ops clk_regmap_vclk_ops; >> + >> +/** >> + * struct clk_regmap_vclk_div_data - vclk_div regmap back specific data >> + * >> + * @offset: offset of the register controlling the divider >> + * @shift: shift to the divider bit field >> + * @width: width of the divider bit field >> + * @enable_bit_idx: single bit controlling vclk divider enable >> + * @reset_bit_idx: single bit controlling vclk divider reset >> + * @table: array of value/divider pairs, last entry should have div = 0 >> + * >> + * Flags: >> + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored >> + */ >> +struct clk_regmap_vclk_div_data { >> + unsigned int offset; >> + u8 shift; >> + u8 width; >> + u8 enable_bit_idx; >> + u8 reset_bit_idx; >> + const struct clk_div_table *table; >> + u8 flags; >> +}; >> + >> +static inline struct clk_regmap_vclk_div_data * >> +clk_get_regmap_vclk_div_data(struct clk_regmap *clk) >> +{ >> + return (struct clk_regmap_vclk_div_data *)clk->data; >> +} >> + >> +extern const struct clk_ops clk_regmap_vclk_div_ops; >> + >> +#endif /* __VCLK_H */ >
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI glue on the same Amlogic SoCs. This is a follow-up of v5 now the DRM patches are applied, the clk & DT changes remains for a full DSI support on G12A & SM1 platforms. The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU pixel reader by the VCLK2 clock using the HDMI PLL. The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. The clock setup has been redesigned to use CCF, a common PLL (GP0) and the VCLK2 clock path for DSI in preparation of full CCF support and possibly dual display with HDMI. The change from v5 is that now we use a "VCLK" driver instea dof notifier and rely on CLK_SET_RATE_GATE to ensure the VCLK gate operation are called. Depends on clkid public migration at [4]. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v7: - Added review tags - Fixed patch 5 thanks to George - Link to v6: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v6-0-fd2ac9845472@linaro.org Changes in v6: - dropped applied DRM patches - dropped clk private prefix patches - rebased on top of 20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org - re-ordered/cleaned ENCL patches to match clkid public migration - Added new "vclk" driver - uses vclk driver instead of notifier - cleaned VCLK2 clk flags - add px_clk gating from DSI driver - Link to v5: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org Changes in v5: - Aded PRIV all the G12 internal clk IDS to simplify public exposing - Fixed the DSI bindings - Fixed the DSI HSYNC/VSYNC polarity handling - Fixed the DSI clock setup - Fixed the DSI phy timings - Dropped components for DSI, only keeping it for HDMI - Added MNT Reform 2 CM4 DT - Dropped already applied PHY fix - Link to v4: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v4-0-2592c29ea263@linaro.org Changes from v3 at [3]: - switched all clk setup via CCF - using single PLL for DSI controller & ENCL encoder - added ENCL clocks to CCF - make the VCLK2 clocks configuration by CCF - fixed probe/bind of DSI controller to work with panels & bridges - added bit_clk to controller to it can setup the BIT clock aswell - added fix for components unbind - added fix for analog phy setup value - added TS050 timings fix - dropped previous clk control patch Changes from v2 at [2]: - Fixed patch 3 - Added reviews from Jagan - Rebased on v5.19-rc1 Changes from v1 at [1]: - fixed DSI host bindings - add reviewed-by tags for bindings - moved magic values to defines thanks to Martin's searches - added proper prefixes to defines - moved phy_configure to phy_init() dw-mipi-dsi callback - moved phy_on to a new phy_power_on() dw-mipi-dsi callback - correctly return phy_init/configure errors to callback returns [1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com [2] https://lore.kernel.org/r/20220120083357.1541262-1-narmstrong@baylibre.com [3] https://lore.kernel.org/r/20220617072723.1742668-1-narmstrong@baylibre.com [4] https://lore.kernel.org/all/20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org/ --- Neil Armstrong (9): dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks clk: meson: add vclk driver clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF drm/meson: gate px_clk when setting rate arm64: meson: g12-common: add the MIPI DSI nodes DONOTMERGE: arm64: meson: khadas-vim3l: add DSI panel dt-bindings: arm: amlogic: Document the MNT Reform 2 CM4 adapter with a BPI-CM4 Module arm64: dts: amlogic: meson-g12b-bananapi-cm4: add support for MNT Reform2 with CM4 adaper Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 ++++ .../meson-g12b-bananapi-cm4-mnt-reform2.dts | 388 +++++++++++++++++++++ .../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 76 ++++ .../boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 2 +- drivers/clk/meson/Kconfig | 5 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/g12a.c | 81 ++++- drivers/clk/meson/vclk.c | 146 ++++++++ drivers/clk/meson/vclk.h | 68 ++++ drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 + include/dt-bindings/clock/g12a-clkc.h | 2 + 14 files changed, 832 insertions(+), 18 deletions(-) --- base-commit: 631ac6d680c1d3bff1a7f29825f11db6889fe958 change-id: 20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-b8e5217e1f4a Best regards,