| Message ID | 20230721221552.1973203-4-contact@jookia.org |
|---|---|
| State | Accepted |
| Commit | 6ea1ad888f5900953a21853e709fa499fdfcb317 |
| Headers | show |
| Series | Add support for Allwinner D1 CAN controllers | expand |
On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote: > ... > + /omit-if-no-ref/ > + can0_pins: can0-pins { > + pins = "PB2", "PB3"; > + function = "can0"; > + }; > ... > + can0: can@2504000 { > + compatible = "allwinner,sun20i-d1-can"; > + reg = <0x02504000 0x400>; > + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CAN0>; > + resets = <&ccu RST_BUS_CAN0>; > + status = "disabled"; > + }; Just a quick late night question to people with more knowledge than me: These chips only have one pinctrl configuration for can0 and can1. Should the can nodes have this pre-set instead of the board dts doing this? I see this happening in sun4i-a10.dtsi for instance, but it also seems like it could become a problem when it comes to re-using the dtsi for newer chip variants. John.
Hi John, Jernej On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote: > ... > @@ -131,6 +131,18 @@ uart3_pb_pins: uart3-pb-pins { > pins = "PB6", "PB7"; > function = "uart3"; > }; > + > + /omit-if-no-ref/ > + can0_pins: can0-pins { > + pins = "PB2", "PB3"; > + function = "can0"; > + }; > + > + /omit-if-no-ref/ > + can1_pins: can1-pins { > + pins = "PB4", "PB5"; > + function = "can1"; > + }; > ... Should we also keep a pinctrl nodes itself in alphabetical order? I mean placing a CAN nodes before `clk_pg11_pin` node? Looks like the other nodes sorted in this way... Cheers, Maksim
On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote: > Hi John, Jernej > Should we also keep a pinctrl nodes itself in alphabetical order? > I mean placing a CAN nodes before `clk_pg11_pin` node? > Looks like the other nodes sorted in this way... Good catch. Now that you mention it, the device tree nodes are sorted by memory order too! These should be after i2c3. It looks like I might need to do a patch to re-order those too. > Cheers, > Maksim John.
Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a): > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote: > > Hi John, Jernej > > Should we also keep a pinctrl nodes itself in alphabetical order? > > I mean placing a CAN nodes before `clk_pg11_pin` node? > > Looks like the other nodes sorted in this way... > > Good catch. Now that you mention it, the device tree nodes are sorted > by memory order too! These should be after i2c3. > > It looks like I might need to do a patch to re-order those too. It would be better if DT patches are dropped from netdev tree and then post new versions. Best regards, Jernej > > > Cheers, > > Maksim > > John.
Dne nedelja, 06. avgust 2023 ob 08:33:45 CEST je John Watts napisal(a): > On Sat, Aug 05, 2023 at 07:49:51PM +0200, Jernej Škrabec wrote: > > Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a): > > > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote: > > > > Hi John, Jernej > > > > Should we also keep a pinctrl nodes itself in alphabetical order? > > > > I mean placing a CAN nodes before `clk_pg11_pin` node? > > > > Looks like the other nodes sorted in this way... > > > > > > Good catch. Now that you mention it, the device tree nodes are sorted > > > by memory order too! These should be after i2c3. > > > > > > It looks like I might need to do a patch to re-order those too. > > > > It would be better if DT patches are dropped from netdev tree and then > > post > > new versions. > > > > Best regards, > > Jernej > > Agreed. Is there a way to request that? Or will the maintainer just read > this? Hopefully it will. Best regards, Jernej
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..4086c0cc0f9d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -131,6 +131,18 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; }; ccu: clock-controller@2001000 { @@ -879,5 +891,23 @@ rtc: rtc@7090000 { clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + status = "disabled"; + }; }; };
The Allwinner D1, T113 provide two CAN controllers that are variants of the R40 controller. I have tested support for these controllers on two boards: - A Lichee Panel RV 86 Panel running a D1 chip - A Mango Pi MQ Dual running a T113-s3 chip Both of these fully support both CAN controllers. Signed-off-by: John Watts <contact@jookia.org> --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+)