| Message ID | 20230711225212.11542-1-palmer@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: RISC-V: Re-word the I extension binding | expand |
On Tue, Jul 11, 2023, at 6:52 PM, Palmer Dabbelt wrote: > I'd argue this changes the definition of the I binding, as there was > more than just the counters that got split out (CSRs and fence.i at > least). We haven't released these bindings yet, so IIUC it's OK to > change the definition still. > > I think this matches the original intent, or at least what the > implementation does. > > Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml > b/Documentation/devicetree/bindings/riscv/extensions.yaml > index cc1f546fdbdc..31ec244bd32f 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -67,13 +67,11 @@ properties: > anyOf: > # single letter extensions, in canonical order > - const: i > - description: | > - The base integer instruction set, as ratified in the > 20191213 > - version of the unprivileged ISA specification. > - > - This does not include Chapter 10, "Counters", which was > moved into > - the Zicntr and Zihpm extensions after the ratification of > the > - 20191213 version of the unprivileged specification. > + description: > + The base integer instruction set, as specified by the 2.2 > + version of the unprivileged ISA specification, formally > known as > + the user-level ISA. This definition of I includes various > + extensions that were later split out. Nitpick: the 2.2 unprivileged ISA uses the pre-ratification memory model (essentially Alpha), which is much weaker than the memory model in 20191213. -s > > - const: m > description: > -- > 2.40.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, Jul 11, 2023 at 03:52:12PM -0700, Palmer Dabbelt wrote: > I'd argue this changes the definition of the I binding, as there was > more than just the counters that got split out (CSRs and fence.i at > least). We haven't released these bindings yet, so IIUC it's OK to > change the definition still. > > I think this matches the original intent, or at least what the > implementation does. Depends on what you consider "original". My intent with these new bindings was to deliberately exclude from `i` things that are already in extensions at the time of writing, so that when an platform shows up that decided not to implement them, it does not need a special case added. I'm fine with doing it this way though, if that is what you want, but what do you mean by "the implementation does"? To align the implementation with the meaning in the current binding, would we need to refuse harts in riscv_early_of_processor_hartid() in Linux? > > Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index cc1f546fdbdc..31ec244bd32f 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -67,13 +67,11 @@ properties: > anyOf: > # single letter extensions, in canonical order > - const: i > - description: | > - The base integer instruction set, as ratified in the 20191213 > - version of the unprivileged ISA specification. > - > - This does not include Chapter 10, "Counters", which was moved into > - the Zicntr and Zihpm extensions after the ratification of the > - 20191213 version of the unprivileged specification. > + description: > + The base integer instruction set, as specified by the 2.2 > + version of the unprivileged ISA specification, formally known as > + the user-level ISA. This definition of I includes various > + extensions that were later split out. > > - const: m > description: > -- > 2.40.1 >
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..31ec244bd32f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -67,13 +67,11 @@ properties: anyOf: # single letter extensions, in canonical order - const: i - description: | - The base integer instruction set, as ratified in the 20191213 - version of the unprivileged ISA specification. - - This does not include Chapter 10, "Counters", which was moved into - the Zicntr and Zihpm extensions after the ratification of the - 20191213 version of the unprivileged specification. + description: + The base integer instruction set, as specified by the 2.2 + version of the unprivileged ISA specification, formally known as + the user-level ISA. This definition of I includes various + extensions that were later split out. - const: m description:
I'd argue this changes the definition of the I binding, as there was more than just the counters that got split out (CSRs and fence.i at least). We haven't released these bindings yet, so IIUC it's OK to change the definition still. I think this matches the original intent, or at least what the implementation does. Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> --- .../devicetree/bindings/riscv/extensions.yaml | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-)