diff mbox series

[v2,18/19] hw/timer/arm_timer: Map ARM_TIMER MMIO regions into IntegratorPIT

Message ID 20230704145012.49870-19-philmd@linaro.org
State New
Headers show
Series hw/timer/arm_timer: QOM'ify ARM_TIMER and correct sysbus/irq in ICP_PIT | expand

Commit Message

Philippe Mathieu-Daudé July 4, 2023, 2:50 p.m. UTC 
Instead of manually forwarding MMIO accesses to each ARM_TIMER,
let have the generic memory code dispatch that for us.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/timer/arm_timer.c | 43 ++++---------------------------------------
 1 file changed, 4 insertions(+), 39 deletions(-)

Comments

Richard Henderson July 5, 2023, 3:44 p.m. UTC | #1 
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
> Instead of manually forwarding MMIO accesses to each ARM_TIMER,
> let have the generic memory code dispatch that for us.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   hw/timer/arm_timer.c | 43 ++++---------------------------------------
>   1 file changed, 4 insertions(+), 39 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index 8207723ab5..7b455aff4d 100644
--- a/hw/timer/arm_timer.c
+++ b/hw/timer/arm_timer.c
@@ -393,6 +393,7 @@  static void sp804_class_init(ObjectClass *klass, void *data)
 }
 
 /* Integrator/CP timer module.  */
+/* ??? Don't know the PrimeCell ID for this device.  */
 
 #define TYPE_INTEGRATOR_PIT "integrator_pit"
 OBJECT_DECLARE_SIMPLE_TYPE(IntegratorPIT, INTEGRATOR_PIT)
@@ -405,43 +406,6 @@  struct IntegratorPIT {
     qemu_irq irq[3];
 };
 
-static uint64_t icp_pit_read(void *opaque, hwaddr offset,
-                             unsigned size)
-{
-    IntegratorPIT *s = opaque;
-    int n;
-
-    /* ??? Don't know the PrimeCell ID for this device.  */
-    n = offset >> 8;
-    if (n > 2) {
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
-        return 0;
-    }
-
-    return arm_timer_read(&s->timer[n], offset & 0xff, size);
-}
-
-static void icp_pit_write(void *opaque, hwaddr offset,
-                          uint64_t value, unsigned size)
-{
-    IntegratorPIT *s = opaque;
-    int n;
-
-    n = offset >> 8;
-    if (n > 2) {
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
-        return;
-    }
-
-    arm_timer_write(&s->timer[n], offset & 0xff, value, size);
-}
-
-static const MemoryRegionOps icp_pit_ops = {
-    .read = icp_pit_read,
-    .write = icp_pit_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
 static void icp_pit_fwd_irq(void *opaque, int n, int level)
 {
     IntegratorPIT *s = opaque;
@@ -469,8 +433,7 @@  static void icp_pit_init(Object *obj)
         sysbus_init_irq(dev, &s->irq[i]);
     }
 
-    memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s,
-                          "icp_pit", 0x1000);
+    memory_region_init(&s->iomem, obj, "icp_pit", 0x1000);
     sysbus_init_mmio(dev, &s->iomem);
     /* This device has no state to save/restore.  The component timers will
        save themselves.  */
@@ -487,6 +450,8 @@  static void icp_pit_realize(DeviceState *dev, Error **errp)
             return;
         }
         sysbus_connect_irq(tmr, 0, qdev_get_gpio_in_named(dev, "timer-in", i));
+        memory_region_add_subregion(&s->iomem, 0x100 * i,
+                                    sysbus_mmio_get_region(tmr, 0));
     }
 }