| Message ID | 20230704163634.3188465-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 7/4/23 18:36, Peter Maydell wrote: > docs/system/arm/sbsa.rst | 5 +- > hw/arm/sbsa-ref.c | 23 +++-- > hw/misc/allwinner-sramc.c | 1 + > target/arm/cpu.c | 65 ++++++++----- > target/arm/gdbstub.c | 4 + > target/arm/helper.c | 70 +++++++++++--- > target/arm/tcg/translate-sme.c | 24 +++-- > target/xtensa/exc_helper.c | 3 + > tests/qtest/xlnx-canfd-test.c | 33 +++---- > tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++++++++++ > tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++ > hw/arm/Kconfig | 2 +- > tests/tcg/aarch64/Makefile.target | 13 ++- > 13 files changed, 436 insertions(+), 79 deletions(-) There's one more failure: https://gitlab.com/qemu-project/qemu/-/jobs/4592433432#L3723 > /tmp/ccASXpLo.s: Assembler messages: > /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name 'id_aa64zfr0_el1' > /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name 'id_aa64smfr0_el1' > make[1]: *** [Makefile:119: sysregs] Error 1 I guess it's the change to Makefile.target, as I don't see any other likely candidates. r~
On 7/5/23 06:57, Richard Henderson wrote: > On 7/4/23 18:36, Peter Maydell wrote: >> docs/system/arm/sbsa.rst | 5 +- >> hw/arm/sbsa-ref.c | 23 +++-- >> hw/misc/allwinner-sramc.c | 1 + >> target/arm/cpu.c | 65 ++++++++----- >> target/arm/gdbstub.c | 4 + >> target/arm/helper.c | 70 +++++++++++--- >> target/arm/tcg/translate-sme.c | 24 +++-- >> target/xtensa/exc_helper.c | 3 + >> tests/qtest/xlnx-canfd-test.c | 33 +++---- >> tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++++++++++ >> tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++ >> hw/arm/Kconfig | 2 +- >> tests/tcg/aarch64/Makefile.target | 13 ++- >> 13 files changed, 436 insertions(+), 79 deletions(-) > > There's one more failure: > > https://gitlab.com/qemu-project/qemu/-/jobs/4592433432#L3723 > >> /tmp/ccASXpLo.s: Assembler messages: >> /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name >> 'id_aa64zfr0_el1' >> /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name >> 'id_aa64smfr0_el1' >> make[1]: *** [Makefile:119: sysregs] Error 1 > > I guess it's the change to Makefile.target, as I don't see any other likely candidates. Ho hum, that's *my* patch 5, "Fix SME full tile indexing". I'll have a closer look tomorrow. Sorry about that. r~
On Wed, 5 Jul 2023 at 06:04, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 7/5/23 06:57, Richard Henderson wrote: > > https://gitlab.com/qemu-project/qemu/-/jobs/4592433432#L3723 > > > >> /tmp/ccASXpLo.s: Assembler messages: > >> /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name > >> 'id_aa64zfr0_el1' > >> /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name > >> 'id_aa64smfr0_el1' > >> make[1]: *** [Makefile:119: sysregs] Error 1 > > > > I guess it's the change to Makefile.target, as I don't see any other likely candidates. > > Ho hum, that's *my* patch 5, "Fix SME full tile indexing". > I'll have a closer look tomorrow. Sorry about that. I think we can fix this by using the S3_.... syntax instead, and we can drop the #ifdef HAS_ARMV9_SME entirely: these registers are in the ID register space so they will read-as-zero and pass the test regardless of guest CPU type. However, it doesn't look like I can run this CI job under my personal gitlab account, so I'll have to do a blind attempt at a fix and resubmit the pullreq for you to see... thanks -- PMM
Just a collection of bug fixes this time around... thanks -- PMM The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de: Merge tag 'pull-maintainer-ominbus-030723-1' of https://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230704 for you to fetch changes up to 86a78272f094857b4eda79d721c116e93942aa9a: target/xtensa: Assert that interrupt level is within bounds (2023-07-04 14:27:08 +0100) ---------------------------------------------------------------- target-arm queue: * Add raw_writes ops for register whose write induce TLB maintenance * hw/arm/sbsa-ref: use XHCI to replace EHCI * Avoid splitting Zregs across lines in dump * Dump ZA[] when active * Fix SME full tile indexing * Handle IC IVAU to improve compatibility with JITs * xlnx-canfd-test: Fix code coverity issues * gdbstub: Guard M-profile code with CONFIG_TCG * allwinner-sramc: Set class_size * target/xtensa: Assert that interrupt level is within bounds ---------------------------------------------------------------- Akihiko Odaki (1): hw: arm: allwinner-sramc: Set class_size Eric Auger (1): target/arm: Add raw_writes ops for register whose write induce TLB maintenance Fabiano Rosas (1): target/arm: gdbstub: Guard M-profile code with CONFIG_TCG John Högberg (2): target/arm: Handle IC IVAU to improve compatibility with JITs tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code Peter Maydell (1): target/xtensa: Assert that interrupt level is within bounds Richard Henderson (3): target/arm: Avoid splitting Zregs across lines in dump target/arm: Dump ZA[] when active target/arm: Fix SME full tile indexing Vikram Garhwal (1): tests/qtest: xlnx-canfd-test: Fix code coverity issues Yuquan Wang (1): hw/arm/sbsa-ref: use XHCI to replace EHCI docs/system/arm/sbsa.rst | 5 +- hw/arm/sbsa-ref.c | 23 +++-- hw/misc/allwinner-sramc.c | 1 + target/arm/cpu.c | 65 ++++++++----- target/arm/gdbstub.c | 4 + target/arm/helper.c | 70 +++++++++++--- target/arm/tcg/translate-sme.c | 24 +++-- target/xtensa/exc_helper.c | 3 + tests/qtest/xlnx-canfd-test.c | 33 +++---- tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++++++++++ tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++ hw/arm/Kconfig | 2 +- tests/tcg/aarch64/Makefile.target | 13 ++- 13 files changed, 436 insertions(+), 79 deletions(-) create mode 100644 tests/tcg/aarch64/icivau.c create mode 100644 tests/tcg/aarch64/sme-outprod1.c