| Message ID | 20230704130647.2842917-2-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement Cortex Neoverse-V1 | expand |
Peter Maydell <peter.maydell@linaro.org> writes: > We already squash the ID register field for FEAT_SPE (the Statistical > Profiling Extension) because TCG does not implement it and if we > advertise it to the guest the guest will crash trying to look at > non-existent system registers. Do the same for some other features > which a real hardware Neoverse-V1 implements but which TCG doesn't: > * FEAT_TRF (Self-hosted Trace Extension) > * Trace Macrocell system register access > * Memory mapped trace > * FEAT_AMU (Activity Monitors Extension) > * FEAT_MPAM (Memory Partitioning and Monitoring Extension) > * FEAT_NV (Nested Virtualization) > > Most of these, like FEAT_SPE, are "introspection/trace" type features > which QEMU is unlikely to ever implement. The odd-one-out here is > FEAT_NV -- we could implement that and at some point we probably > will. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
On 7/4/23 15:06, Peter Maydell wrote: > We already squash the ID register field for FEAT_SPE (the Statistical > Profiling Extension) because TCG does not implement it and if we > advertise it to the guest the guest will crash trying to look at > non-existent system registers. Do the same for some other features > which a real hardware Neoverse-V1 implements but which TCG doesn't: > * FEAT_TRF (Self-hosted Trace Extension) > * Trace Macrocell system register access > * Memory mapped trace > * FEAT_AMU (Activity Monitors Extension) > * FEAT_MPAM (Memory Partitioning and Monitoring Extension) > * FEAT_NV (Nested Virtualization) > > Most of these, like FEAT_SPE, are "introspection/trace" type features > which QEMU is unlikely to ever implement. The odd-one-out here is > FEAT_NV -- we could implement that and at some point we probably > will. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/cpu.c | 33 +++++++++++++++++++++++++++++---- > 1 file changed, 29 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1e77698ba2..7eb7e909097 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2048,13 +2048,38 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (tcg_enabled()) { /* - * Don't report the Statistical Profiling Extension in the ID - * registers, because TCG doesn't implement it yet (not even a - * minimal stub version) and guests will fall over when they - * try to access the non-existent system registers for it. + * Don't report some architectural features in the ID registers + * where TCG does not yet implement it (not even a minimal + * stub version). This avoids guests falling over when they + * try to access the non-existent system registers for them. */ + /* FEAT_SPE (Statistical Profiling Extension) */ cpu->isar.id_aa64dfr0 = FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + /* FEAT_TRF (Self-hosted Trace Extension) */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + /* Trace Macrocell system register access */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + /* Memory mapped trace */ + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + /* FEAT_AMU (Activity Monitors Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + cpu->isar.id_pfr0 = + FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + /* FEAT_NV (Nested Virtualization) */ + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); } /* MPU can be configured out of a PMSA CPU either by setting has-mpu
We already squash the ID register field for FEAT_SPE (the Statistical Profiling Extension) because TCG does not implement it and if we advertise it to the guest the guest will crash trying to look at non-existent system registers. Do the same for some other features which a real hardware Neoverse-V1 implements but which TCG doesn't: * FEAT_TRF (Self-hosted Trace Extension) * Trace Macrocell system register access * Memory mapped trace * FEAT_AMU (Activity Monitors Extension) * FEAT_MPAM (Memory Partitioning and Monitoring Extension) * FEAT_NV (Nested Virtualization) Most of these, like FEAT_SPE, are "introspection/trace" type features which QEMU is unlikely to ever implement. The odd-one-out here is FEAT_NV -- we could implement that and at some point we probably will. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-)