| Message ID | 20230621043628.21485-9-quic_kriskura@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
On 21.06.2023 06:36, Krishna Kurapati wrote: > Add USB and DWC3 node for tertiary port of SC8280 along with multiport > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > platforms. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 8fa9fbfe5d00..0dfa350ea3b3 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -3013,6 +3013,83 @@ system-cache-controller@9200000 { > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > > + usb_2: usb@a4f8800 { > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; > + reg = <0 0x0a4f8800 0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; These three properties, please stick just before status > + > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_SLEEP_CLK>, > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; Please make it one per line > + > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; And here > + > + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > + <&pdc 129 IRQ_TYPE_EDGE_RISING>, > + <&pdc 128 IRQ_TYPE_EDGE_RISING>, > + <&pdc 131 IRQ_TYPE_EDGE_RISING>, > + <&pdc 130 IRQ_TYPE_EDGE_RISING>, > + <&pdc 133 IRQ_TYPE_EDGE_RISING>, > + <&pdc 132 IRQ_TYPE_EDGE_RISING>, > + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, Not a comment to the patch, but very nice that Qcom ensured every endpoint is wakeup-capable, this used not to be the case before :D > + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; > + Remove this newline > + interrupt-names = "dp1_hs_phy_irq", "dm1_hs_phy_irq", > + "dp2_hs_phy_irq", "dm2_hs_phy_irq", > + "dp3_hs_phy_irq", "dm3_hs_phy_irq", > + "dp4_hs_phy_irq", "dm4_hs_phy_irq", > + "ss1_phy_irq", "ss2_phy_irq", > + "pwr_event_1", > + "pwr_event_2", > + "pwr_event_3", > + "pwr_event_4"; Please make it one per line > + > + power-domains = <&gcc USB30_MP_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + resets = <&gcc GCC_USB30_MP_BCR>; > + > + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > + wakeup-source; > + > + status = "disabled"; > + > + usb_2_dwc3: usb@a400000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a400000 0 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x800 0x0>; > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, > + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, > + <&usb_2_hsphy2>, > + <&usb_2_hsphy3>; And here > + phy-names = "usb2-port0", "usb3-port0", > + "usb2-port1", "usb3-port1", > + "usb2-port2", > + "usb2-port3"; And here Thanks for working on this! Konrad > + }; > + }; > + > usb_0: usb@a6f8800 { > compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; > reg = <0 0x0a6f8800 0 0x400>;
On 6/24/2023 4:09 AM, Konrad Dybcio wrote: > On 21.06.2023 06:36, Krishna Kurapati wrote: >> Add USB and DWC3 node for tertiary port of SC8280 along with multiport >> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride >> platforms. >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> index 8fa9fbfe5d00..0dfa350ea3b3 100644 >> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> @@ -3013,6 +3013,83 @@ system-cache-controller@9200000 { >> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> + usb_2: usb@a4f8800 { >> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; >> + reg = <0 0x0a4f8800 0 0x400>; > >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; > These three properties, please stick just before status > >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, >> + <&gcc GCC_USB30_MP_MASTER_CLK>, >> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, >> + <&gcc GCC_USB30_MP_SLEEP_CLK>, >> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, >> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, >> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; >> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", >> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; > Please make it one per line > >> + >> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_MP_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <200000000>; > And here > >> + >> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 126 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 129 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 128 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 131 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 130 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 133 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 132 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > Not a comment to the patch, but very nice that Qcom ensured every > endpoint is wakeup-capable, this used not to be the case before :D Yes wakeup is supported by all ports now, but I didn't make those changes now as I wanted to keep driver code diff minimal and don't need wakeup support for the product currently. But for sure, will update driver code to handle wakeup on all ports in near future. Regards, Krishna, > >> + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; >> + > Remove this newline > >> + interrupt-names = "dp1_hs_phy_irq", "dm1_hs_phy_irq", >> + "dp2_hs_phy_irq", "dm2_hs_phy_irq", >> + "dp3_hs_phy_irq", "dm3_hs_phy_irq", >> + "dp4_hs_phy_irq", "dm4_hs_phy_irq", >> + "ss1_phy_irq", "ss2_phy_irq", >> + "pwr_event_1", >> + "pwr_event_2", >> + "pwr_event_3", >> + "pwr_event_4"; > Please make it one per line > >> + >> + power-domains = <&gcc USB30_MP_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + resets = <&gcc GCC_USB30_MP_BCR>; >> + >> + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; >> + interconnect-names = "usb-ddr", "apps-usb"; >> + >> + wakeup-source; >> + >> + status = "disabled"; >> + >> + usb_2_dwc3: usb@a400000 { >> + compatible = "snps,dwc3"; >> + reg = <0 0x0a400000 0 0xcd00>; >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + iommus = <&apps_smmu 0x800 0x0>; >> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, >> + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, >> + <&usb_2_hsphy2>, >> + <&usb_2_hsphy3>; > And here >> + phy-names = "usb2-port0", "usb3-port0", >> + "usb2-port1", "usb3-port1", >> + "usb2-port2", >> + "usb2-port3"; > And here > > Thanks for working on this! > > Konrad >> + }; >> + }; >> + >> usb_0: usb@a6f8800 { >> compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; >> reg = <0 0x0a6f8800 0 0x400>;
On Sat, Jun 24, 2023 at 12:39:36AM +0200, Konrad Dybcio wrote: > On 21.06.2023 06:36, Krishna Kurapati wrote: > > Add USB and DWC3 node for tertiary port of SC8280 along with multiport > > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > > platforms. > > > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++ > > 1 file changed, 77 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > index 8fa9fbfe5d00..0dfa350ea3b3 100644 > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > @@ -3013,6 +3013,83 @@ system-cache-controller@9200000 { > > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > > }; > > > > + usb_2: usb@a4f8800 { > > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; > > + reg = <0 0x0a4f8800 0 0x400>; > > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > These three properties, please stick just before status No, please keep them were they are for consistency with the rest of the file. > > + > > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, > > + <&gcc GCC_USB30_MP_MASTER_CLK>, > > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, > > + <&gcc GCC_USB30_MP_SLEEP_CLK>, > > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, > > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, > > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, > > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; > > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", > > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; > Please make it one per line Also not needed for the same reason. > > > + > > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB30_MP_MASTER_CLK>; > > + assigned-clock-rates = <19200000>, <200000000>; > And here Same here. Johan
On Sat, Jun 24, 2023 at 12:43:23PM +0530, Krishna Kurapati PSSNV wrote: > > On 21.06.2023 06:36, Krishna Kurapati wrote: > >> Add USB and DWC3 node for tertiary port of SC8280 along with multiport > >> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > >> platforms. > >> > >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > > Not a comment to the patch, but very nice that Qcom ensured every > > endpoint is wakeup-capable, this used not to be the case before :D > Yes wakeup is supported by all ports now, but I didn't make those > changes now as I wanted to keep driver code diff minimal and don't need > wakeup support for the product currently. But for sure, will update > driver code to handle wakeup on all ports in near future. Why didn't you include it in v9? I thought you had a working implementation for this? Since wakeup will be another case where glue and core need to interact, it's good to have the wakeup implementation from the start to be able to evaluate your multiport implementation properly. Right now it looks like you only added wakeup interrupt lookup and request, but then you never actually enable them which is not very nice. Johan
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 8fa9fbfe5d00..0dfa350ea3b3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3013,6 +3013,83 @@ system-cache-controller@9200000 { interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 129 IRQ_TYPE_EDGE_RISING>, + <&pdc 128 IRQ_TYPE_EDGE_RISING>, + <&pdc 131 IRQ_TYPE_EDGE_RISING>, + <&pdc 130 IRQ_TYPE_EDGE_RISING>, + <&pdc 133 IRQ_TYPE_EDGE_RISING>, + <&pdc 132 IRQ_TYPE_EDGE_RISING>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "dp1_hs_phy_irq", "dm1_hs_phy_irq", + "dp2_hs_phy_irq", "dm2_hs_phy_irq", + "dp3_hs_phy_irq", "dm3_hs_phy_irq", + "dp4_hs_phy_irq", "dm4_hs_phy_irq", + "ss1_phy_irq", "ss2_phy_irq", + "pwr_event_1", + "pwr_event_2", + "pwr_event_3", + "pwr_event_4"; + + power-domains = <&gcc USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-port0", "usb3-port0", + "usb2-port1", "usb3-port1", + "usb2-port2", + "usb2-port3"; + }; + }; + usb_0: usb@a6f8800 { compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>;
Add USB and DWC3 node for tertiary port of SC8280 along with multiport IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride platforms. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++ 1 file changed, 77 insertions(+)