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[v3,00/15] Introduce the SC8180x devices

Message ID 20230530162454.51708-1-vkoul@kernel.org
Headers show
Series Introduce the SC8180x devices | expand

Message

Vinod Koul May 30, 2023, 4:24 p.m. UTC 
This introduces Qualcomm SC8180x SoC which features in Lenovo Flex 5G
laptop. This also adds support for Primus platform as well as Lenovo Flex 5G
laptop.

Changes in v3:
 - Split DTS patch into smaller check
 - checkpatch and dtbs check error fixes
 - fix comments from Konrad/Krzysztof

Changes in v2:
 - Fix the ufs pcie and phy bindings
 - Lots of error fixes for dtbs_check
 - Add few more missing compatiables

Bjorn Andersson (3):
  arm64: dts: qcom: Introduce the SC8180x platform
  arm64: dts: qcom: sc8180x: Introduce Primus
  arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G

Vinod Koul (12):
  dt-bindings: PCI: qcom: Fix sc8180x clocks and interrupts
  dt-bindings: usb: qcom,dwc3: Add SC8180x binding
  dt-bindings: interconnect: split SC8180x to own schema
  scsi: ufs: dt-bindings: Add SC8180x binding
  dt-bindings: qcom,pdc: Add SC8180x compatible
  arm64: dts: qcom: sc8180x: Add interconnects and lmh
  arm64: dts: qcom: sc8180x: Add thermal zones
  arm64: dts: qcom: sc8180x: Add QUPs
  arm64: dts: qcom: sc8180x: Add PCIe instances
  arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes
  arm64: dts: qcom: sc8180x: Add display and gpu nodes
  arm64: dts: qcom: sc8180x: Add pmics

 .../bindings/interconnect/qcom,rpmh.yaml      |   11 -
 .../interconnect/qcom,sc8180x-rpmh.yaml       |   49 +
 .../interrupt-controller/qcom,pdc.yaml        |    1 +
 .../devicetree/bindings/pci/qcom,pcie.yaml    |   29 +-
 .../devicetree/bindings/ufs/qcom,ufs.yaml     |    2 +
 .../devicetree/bindings/usb/qcom,dwc3.yaml    |    3 +
 arch/arm64/boot/dts/qcom/Makefile             |    2 +
 .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts  |  583 +++
 arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi   |  326 ++
 arch/arm64/boot/dts/qcom/sc8180x-primus.dts   |  706 +++
 arch/arm64/boot/dts/qcom/sc8180x.dtsi         | 4030 +++++++++++++++++
 11 files changed, 5730 insertions(+), 12 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-primus.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc8180x.dtsi

Comments

Krzysztof Kozlowski May 31, 2023, 8:19 a.m. UTC | #1 
On 30/05/2023 18:24, Vinod Koul wrote:
> Commit 45a3ec891370 ("PCI: qcom: Add sc8180x compatible") added sc8180x
> compatible and commit 075a9d55932e ("dt-bindings: PCI: qcom: Convert to
> YAML") converted the description to yaml
> 
> But there are still some errors specific to sc8180x which this change
> attempts to fix. The clocks and resets for sc8180 pcie controller are
> different so need to be documented separately

I don't get what's the error here to fix. The clocks you list are
already there as part of oneOf.

> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.yaml    | 29 ++++++++++++++++++-
>  1 file changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 81971be4e554..40a1f451a3d3 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -476,6 +476,33 @@ allOf:
>            items:
>              - const: pci # PCIe core reset
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-sc8180x
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 8
> +          maxItems: 8
> +        clock-names:
> +          items:
> +            - const: pipe # PIPE clock
> +            - const: aux # Auxiliary clock
> +            - const: cfg # Configuration clock
> +            - const: bus_master # Master AXI clock
> +            - const: bus_slave # Slave AXI clock
> +            - const: slave_q2a # Slave Q2A clock
> +            - const: ref # REFERENCE clock
> +            - const: tbu # PCIe TBU clock
> +        resets:
> +          maxItems: 1
> +        reset-names:
> +          items:
> +            - const: pci # PCIe core reset
> +
>    - if:
>        properties:
>          compatible:
> @@ -524,7 +551,6 @@ allOf:
>          compatible:
>            contains:
>              enum:
> -              - qcom,pcie-sc8180x
>                - qcom,pcie-sm8150
>                - qcom,pcie-sm8250
>      then:
> @@ -749,6 +775,7 @@ allOf:
>            contains:
>              enum:
>                - qcom,pcie-sa8540p
> +              - qcom,pcie-sc8180x
>                - qcom,pcie-sc8280xp
>      then:
>        required:

Best regards,
Krzysztof
Krzysztof Kozlowski May 31, 2023, 8:22 a.m. UTC | #2 
On 30/05/2023 18:24, Vinod Koul wrote:
> SC8180x comes with interconnects with missing IO address space and
> variable number of clocks, so split it from common file for easier
> maintenance and to fix warnings like:
> 
> sc8180x-lenovo-flex-5g.dtb: interconnect-0: 'reg' is a required property
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../bindings/interconnect/qcom,rpmh.yaml      | 11 -----
>  .../interconnect/qcom,sc8180x-rpmh.yaml       | 49 +++++++++++++++++++
>  2 files changed, 49 insertions(+), 11 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> index 4d93ad415e0b..5cbc3be49e99 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> @@ -39,17 +39,6 @@ properties:
>        - qcom,sc7180-npu-noc
>        - qcom,sc7180-qup-virt
>        - qcom,sc7180-system-noc
> -      - qcom,sc8180x-aggre1-noc
> -      - qcom,sc8180x-aggre2-noc
> -      - qcom,sc8180x-camnoc-virt
> -      - qcom,sc8180x-compute-noc
> -      - qcom,sc8180x-config-noc
> -      - qcom,sc8180x-dc-noc
> -      - qcom,sc8180x-gem-noc
> -      - qcom,sc8180x-mc-virt
> -      - qcom,sc8180x-mmss-noc
> -      - qcom,sc8180x-qup-virt
> -      - qcom,sc8180x-system-noc
>        - qcom,sdm670-aggre1-noc
>        - qcom,sdm670-aggre2-noc
>        - qcom,sdm670-config-noc
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> new file mode 100644
> index 000000000000..b182c2c5addc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/qcom,sc8180x-rpmh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm RPMh Network-On-Chip Interconnect on SC8180X
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@kernel.org>
> +  - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +description: |
> +  RPMh interconnect providers support system bandwidth requirements through
> +  RPMh hardware accelerators known as Bus Clock Manager (BCM).
> +
> +  See also:: include/dt-bindings/interconnect/qcom,sc8180x.h
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,sc8180x-aggre1-noc
> +      - qcom,sc8180x-aggre2-noc
> +      - qcom,sc8180x-camnoc-virt
> +      - qcom,sc8180x-compute-noc
> +      - qcom,sc8180x-config-noc
> +      - qcom,sc8180x-dc-noc
> +      - qcom,sc8180x-gem-noc
> +      - qcom,sc8180x-ipa-virt
> +      - qcom,sc8180x-mc-virt
> +      - qcom,sc8180x-mmss-noc
> +      - qcom,sc8180x-qup-virt
> +      - qcom,sc8180x-system-noc
> +
> +required:
> +  - compatible
> +
> +allOf:
> +  - $ref: qcom,rpmh-common.yaml#

This should be based on sc7280. You need reg for some of the entries.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    interconnect-0 {

Just "interconnect"


> +        compatible = "qcom,sc8180x-camnoc-virt";
> +        #interconnect-cells = <2>;
> +        qcom,bcm-voters = <&apps_bcm_voter>;
> +    };

Best regards,
Krzysztof
Vinod Koul June 1, 2023, 7:21 a.m. UTC | #3 
On 31-05-23, 10:19, Krzysztof Kozlowski wrote:
> On 30/05/2023 18:24, Vinod Koul wrote:
> > Commit 45a3ec891370 ("PCI: qcom: Add sc8180x compatible") added sc8180x
> > compatible and commit 075a9d55932e ("dt-bindings: PCI: qcom: Convert to
> > YAML") converted the description to yaml
> > 
> > But there are still some errors specific to sc8180x which this change
> > attempts to fix. The clocks and resets for sc8180 pcie controller are
> > different so need to be documented separately
> 
> I don't get what's the error here to fix. The clocks you list are
> already there as part of oneOf.

It was listed with sm8150 block which has different set of clocks than
used in sc81880x, so this needs to have its own block of clocks and
resets

> > 
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  .../devicetree/bindings/pci/qcom,pcie.yaml    | 29 ++++++++++++++++++-
> >  1 file changed, 28 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index 81971be4e554..40a1f451a3d3 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -476,6 +476,33 @@ allOf:
> >            items:
> >              - const: pci # PCIe core reset
> >  
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - qcom,pcie-sc8180x
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 8
> > +          maxItems: 8
> > +        clock-names:
> > +          items:
> > +            - const: pipe # PIPE clock
> > +            - const: aux # Auxiliary clock
> > +            - const: cfg # Configuration clock
> > +            - const: bus_master # Master AXI clock
> > +            - const: bus_slave # Slave AXI clock
> > +            - const: slave_q2a # Slave Q2A clock
> > +            - const: ref # REFERENCE clock
> > +            - const: tbu # PCIe TBU clock
> > +        resets:
> > +          maxItems: 1
> > +        reset-names:
> > +          items:
> > +            - const: pci # PCIe core reset
> > +
> >    - if:
> >        properties:
> >          compatible:
> > @@ -524,7 +551,6 @@ allOf:
> >          compatible:
> >            contains:
> >              enum:
> > -              - qcom,pcie-sc8180x
> >                - qcom,pcie-sm8150
> >                - qcom,pcie-sm8250
> >      then:
> > @@ -749,6 +775,7 @@ allOf:
> >            contains:
> >              enum:
> >                - qcom,pcie-sa8540p
> > +              - qcom,pcie-sc8180x
> >                - qcom,pcie-sc8280xp
> >      then:
> >        required:
> 
> Best regards,
> Krzysztof
Vinod Koul June 1, 2023, 7:23 a.m. UTC | #4 
On 31-05-23, 10:22, Krzysztof Kozlowski wrote:
> On 30/05/2023 18:24, Vinod Koul wrote:
> > SC8180x comes with interconnects with missing IO address space and
> > variable number of clocks, so split it from common file for easier
> > maintenance and to fix warnings like:
> > 
> > sc8180x-lenovo-flex-5g.dtb: interconnect-0: 'reg' is a required property
> > 
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  .../bindings/interconnect/qcom,rpmh.yaml      | 11 -----
> >  .../interconnect/qcom,sc8180x-rpmh.yaml       | 49 +++++++++++++++++++
> >  2 files changed, 49 insertions(+), 11 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> > index 4d93ad415e0b..5cbc3be49e99 100644
> > --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> > +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> > @@ -39,17 +39,6 @@ properties:
> >        - qcom,sc7180-npu-noc
> >        - qcom,sc7180-qup-virt
> >        - qcom,sc7180-system-noc
> > -      - qcom,sc8180x-aggre1-noc
> > -      - qcom,sc8180x-aggre2-noc
> > -      - qcom,sc8180x-camnoc-virt
> > -      - qcom,sc8180x-compute-noc
> > -      - qcom,sc8180x-config-noc
> > -      - qcom,sc8180x-dc-noc
> > -      - qcom,sc8180x-gem-noc
> > -      - qcom,sc8180x-mc-virt
> > -      - qcom,sc8180x-mmss-noc
> > -      - qcom,sc8180x-qup-virt
> > -      - qcom,sc8180x-system-noc
> >        - qcom,sdm670-aggre1-noc
> >        - qcom,sdm670-aggre2-noc
> >        - qcom,sdm670-config-noc
> > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> > new file mode 100644
> > index 000000000000..b182c2c5addc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8180x-rpmh.yaml
> > @@ -0,0 +1,49 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interconnect/qcom,sc8180x-rpmh.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm RPMh Network-On-Chip Interconnect on SC8180X
> > +
> > +maintainers:
> > +  - Bjorn Andersson <andersson@kernel.org>
> > +  - Konrad Dybcio <konrad.dybcio@linaro.org>
> > +
> > +description: |
> > +  RPMh interconnect providers support system bandwidth requirements through
> > +  RPMh hardware accelerators known as Bus Clock Manager (BCM).
> > +
> > +  See also:: include/dt-bindings/interconnect/qcom,sc8180x.h
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,sc8180x-aggre1-noc
> > +      - qcom,sc8180x-aggre2-noc
> > +      - qcom,sc8180x-camnoc-virt
> > +      - qcom,sc8180x-compute-noc
> > +      - qcom,sc8180x-config-noc
> > +      - qcom,sc8180x-dc-noc
> > +      - qcom,sc8180x-gem-noc
> > +      - qcom,sc8180x-ipa-virt
> > +      - qcom,sc8180x-mc-virt
> > +      - qcom,sc8180x-mmss-noc
> > +      - qcom,sc8180x-qup-virt
> > +      - qcom,sc8180x-system-noc
> > +
> > +required:
> > +  - compatible
> > +
> > +allOf:
> > +  - $ref: qcom,rpmh-common.yaml#
> 
> This should be based on sc7280. You need reg for some of the entries.

Yes missed reg part here.

Question is should it be added sc7280 or have a different file, I think
doing former is better

> 
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    interconnect-0 {
> 
> Just "interconnect"

Nope. We have multiple virtual nodes here so interconnect-N would
need to be done
Krzysztof Kozlowski June 1, 2023, 7:25 a.m. UTC | #5 
On 01/06/2023 09:21, Vinod Koul wrote:
> On 31-05-23, 10:19, Krzysztof Kozlowski wrote:
>> On 30/05/2023 18:24, Vinod Koul wrote:
>>> Commit 45a3ec891370 ("PCI: qcom: Add sc8180x compatible") added sc8180x
>>> compatible and commit 075a9d55932e ("dt-bindings: PCI: qcom: Convert to
>>> YAML") converted the description to yaml
>>>
>>> But there are still some errors specific to sc8180x which this change
>>> attempts to fix. The clocks and resets for sc8180 pcie controller are
>>> different so need to be documented separately
>>
>> I don't get what's the error here to fix. The clocks you list are
>> already there as part of oneOf.
> 
> It was listed with sm8150 block which has different set of clocks than
> used in sc81880x, so this needs to have its own block of clocks and
> resets


Ah, after careful check I see indeed difference in one clock.

Best regards,
Krzysztof
Krzysztof Kozlowski June 1, 2023, 7:26 a.m. UTC | #6 
On 30/05/2023 18:24, Vinod Koul wrote:
> Commit 45a3ec891370 ("PCI: qcom: Add sc8180x compatible") added sc8180x
> compatible and commit 075a9d55932e ("dt-bindings: PCI: qcom: Convert to
> YAML") converted the description to yaml
> 
> But there are still some errors specific to sc8180x which this change
> attempts to fix. The clocks and resets for sc8180 pcie controller are
> different so need to be documented separately
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Krzysztof Kozlowski June 1, 2023, 7:26 a.m. UTC | #7 
On 01/06/2023 09:23, Vinod Koul wrote:
>>
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    interconnect-0 {
>>
>> Just "interconnect"
> 
> Nope. We have multiple virtual nodes here so interconnect-N would
> need to be done
> 

You don't have. You have only one node here.
Best regards,
Krzysztof