Message ID | 20230523213825.120077-2-macroalpha82@gmail.com |
---|---|
State | New |
Headers | show |
Series | [1/6] ASoC: es8328: Enabling support for 12Mhz sysclk | expand |
On Tue, May 23, 2023 at 04:38:20PM -0500, Chris Morgan wrote: > +static unsigned int ratios_12000[] = { > + 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, > + 48000, 88235, 96000, > +}; > + > +static struct snd_pcm_hw_constraint_list constraints_12000 = { > + .count = ARRAY_SIZE(ratios_12000), > + .list = ratios_12000, > +}; ... > + case 12000000: > + es8328->sysclk_constraints = &constraints_12000; > + es8328->mclk_ratios = ratios_12000; The other constraints have separate rates and ratios, with wildly different values between the two - the ratio (I'm guessing a clock divider) being written to a 5 bit field which obviously can't contain the actual sample rate.
On Wed, May 24, 2023 at 12:57:02PM +0100, Mark Brown wrote: > On Tue, May 23, 2023 at 04:38:20PM -0500, Chris Morgan wrote: > > > +static unsigned int ratios_12000[] = { > > + 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, > > + 48000, 88235, 96000, > > +}; > > + > > +static struct snd_pcm_hw_constraint_list constraints_12000 = { > > + .count = ARRAY_SIZE(ratios_12000), > > + .list = ratios_12000, > > +}; > > ... > > > + case 12000000: > > + es8328->sysclk_constraints = &constraints_12000; > > + es8328->mclk_ratios = ratios_12000; > > The other constraints have separate rates and ratios, with wildly > different values between the two - the ratio (I'm guessing a clock > divider) being written to a 5 bit field which obviously can't contain > the actual sample rate. A bit over my head here, I saw this patch from the Rockchip BSP kernel branch and tested it on my mainline kernel. Long story short the clock for the mclk is 12000000. I see that there are similar issues for the ES8316 on the Rock 5B, so I will probably just wait for a proper fix there and then implement something similar here. Thank you.
On Wed, May 24, 2023 at 11:12:49AM -0500, Chris Morgan wrote: > On Wed, May 24, 2023 at 12:57:02PM +0100, Mark Brown wrote: > > The other constraints have separate rates and ratios, with wildly > > different values between the two - the ratio (I'm guessing a clock > > divider) being written to a 5 bit field which obviously can't contain > > the actual sample rate. > A bit over my head here, I saw this patch from the Rockchip BSP kernel > branch and tested it on my mainline kernel. Long story short the clock > for the mclk is 12000000. I see that there are similar issues for the > ES8316 on the Rock 5B, so I will probably just wait for a proper fix > there and then implement something similar here. It sounded from the rest of the series like you don't actually want to run at 12MHz anyway, you want a change which deconfigures the sysclk when the card is idle - that'd allow it to be reconfigured as needed to support the widest possible set of rates. That'd be work in the generic cards.
diff --git a/sound/soc/codecs/es8328.c b/sound/soc/codecs/es8328.c index 160adc706cc6..3918be5fc3f1 100644 --- a/sound/soc/codecs/es8328.c +++ b/sound/soc/codecs/es8328.c @@ -36,6 +36,16 @@ static const struct snd_pcm_hw_constraint_list constraints_12288 = { .list = rates_12288, }; +static unsigned int ratios_12000[] = { + 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, + 48000, 88235, 96000, +}; + +static struct snd_pcm_hw_constraint_list constraints_12000 = { + .count = ARRAY_SIZE(ratios_12000), + .list = ratios_12000, +}; + static const unsigned int rates_11289[] = { 8018, 11025, 22050, 44100, 88200, }; @@ -577,6 +587,13 @@ static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, es8328->sysclk_constraints = &constraints_12288; es8328->mclk_ratios = ratios_12288; break; + case 24000000: + mclkdiv2 = 1; + fallthrough; + case 12000000: + es8328->sysclk_constraints = &constraints_12000; + es8328->mclk_ratios = ratios_12000; + break; default: return -EINVAL; }