| Message ID | 20230519214813.2593271-8-bhupesh.sharma@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: Enable Crypto Engine for a few Qualcomm SoCs | expand |
On Sat, May 20, 2023 at 03:18:09AM +0530, Bhupesh Sharma wrote: > Add crypto engine (CE) and CE BAM related nodes and definitions to > 'sm6115.dtsi'. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Tested-by: Anders Roxell <anders.roxell@linaro.org> > Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 631ca327e064..27ff42cf6066 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 { > status = "disabled"; > }; > > + cryptobam: dma-controller@1b04000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0x0 0x01b04000 0x0 0x24000>; > + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <8>; > + qcom,num-ees = <2>; I would also add the RPM_SMD_CE1_CLK clock here and then omit "num-channels" and "qcom,num-ees" (with [1]). It's not strictly necessary but will guarantee that the clock is running whenever the BAM is accessed (potentially avoiding crashes). And it seems to be the typical approach so far, see e.g. sdm845. RPMH_CE_CLK is used on both &cryptobam and &crypto there. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commit/?id=8975dd41a9dbca3b47f7b8dac5bc4dfb23011000 Thanks, Stephan
On Wed, 24 May 2023 at 23:53, Stephan Gerhold <stephan@gerhold.net> wrote: > > On Sat, May 20, 2023 at 03:18:09AM +0530, Bhupesh Sharma wrote: > > Add crypto engine (CE) and CE BAM related nodes and definitions to > > 'sm6115.dtsi'. > > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Tested-by: Anders Roxell <anders.roxell@linaro.org> > > Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm6115.dtsi | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > index 631ca327e064..27ff42cf6066 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 { > > status = "disabled"; > > }; > > > > + cryptobam: dma-controller@1b04000 { > > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > > + reg = <0x0 0x01b04000 0x0 0x24000>; > > + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + qcom,ee = <0>; > > + qcom,controlled-remotely; > > + num-channels = <8>; > > + qcom,num-ees = <2>; > > I would also add the RPM_SMD_CE1_CLK clock here and then omit > "num-channels" and "qcom,num-ees" (with [1]). It's not strictly > necessary but will guarantee that the clock is running whenever the BAM > is accessed (potentially avoiding crashes). And it seems to be the > typical approach so far, see e.g. sdm845. RPMH_CE_CLK is used on both > &cryptobam and &crypto there. > > [1]: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commit/?id=8975dd41a9dbca3b47f7b8dac5bc4dfb23011000 Sure, I have fixed this in v8 which I will post shortly. Thanks, Bhupesh
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 631ca327e064..27ff42cf6066 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 { status = "disabled"; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>; + }; + qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; reg = <0x0 0x01b40000 0x0 0x7000>;