| Message ID | 20230503085657.1814850-12-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand |
On 5/3/23 05:56, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > tcg/riscv/tcg-target-con-set.h | 1 + > tcg/riscv/tcg-target.h | 8 ++++---- > tcg/riscv/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++ > 3 files changed, 40 insertions(+), 4 deletions(-) > > diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h > index a5cadd303f..aac5ceee2b 100644 > --- a/tcg/riscv/tcg-target-con-set.h > +++ b/tcg/riscv/tcg-target-con-set.h > @@ -18,5 +18,6 @@ C_O1_I2(r, r, rI) > C_O1_I2(r, r, rJ) > C_O1_I2(r, rZ, rN) > C_O1_I2(r, rZ, rZ) > +C_N1_I2(r, r, rM) > C_O1_I4(r, r, rI, rM, rM) > C_O2_I4(r, r, rZ, rZ, rM, rM) > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index e9e84be9a5..cff5de5c9e 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -125,8 +125,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_eqv_i32 have_zbb > #define TCG_TARGET_HAS_nand_i32 0 > #define TCG_TARGET_HAS_nor_i32 0 > -#define TCG_TARGET_HAS_clz_i32 0 > -#define TCG_TARGET_HAS_ctz_i32 0 > +#define TCG_TARGET_HAS_clz_i32 1 > +#define TCG_TARGET_HAS_ctz_i32 1 > #define TCG_TARGET_HAS_ctpop_i32 have_zbb > #define TCG_TARGET_HAS_brcond2 1 > #define TCG_TARGET_HAS_setcond2 1 > @@ -159,8 +159,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_eqv_i64 have_zbb > #define TCG_TARGET_HAS_nand_i64 0 > #define TCG_TARGET_HAS_nor_i64 0 > -#define TCG_TARGET_HAS_clz_i64 0 > -#define TCG_TARGET_HAS_ctz_i64 0 > +#define TCG_TARGET_HAS_clz_i64 1 > +#define TCG_TARGET_HAS_ctz_i64 1 > #define TCG_TARGET_HAS_ctpop_i64 have_zbb > #define TCG_TARGET_HAS_add2_i64 1 > #define TCG_TARGET_HAS_sub2_i64 1 > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 1c57b64182..a1c92b0603 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1063,6 +1063,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, > } > } > > +static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, > + TCGReg ret, TCGReg src1, int src2, bool c_src2) > +{ > + tcg_out_opc_imm(s, insn, ret, src1, 0); > + > + if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { > + /* > + * The requested zero result does not match the insn, so adjust. > + * Note that constraints put 'ret' in a new register, so the > + * computation above did not clobber either 'src1' or 'src2'. > + */ > + tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true, > + src2, c_src2, ret, false); > + } > +} > + > static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) > { > TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; > @@ -1724,6 +1740,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); > break; > > + case INDEX_op_clz_i32: > + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2); > + break; > + case INDEX_op_clz_i64: > + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2); > + break; > + case INDEX_op_ctz_i32: > + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2); > + break; > + case INDEX_op_ctz_i64: > + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2); > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1917,6 +1946,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_rotr_i64: > return C_O1_I2(r, r, ri); > > + case INDEX_op_clz_i32: > + case INDEX_op_clz_i64: > + case INDEX_op_ctz_i32: > + case INDEX_op_ctz_i64: > + return C_N1_I2(r, r, rM); > + > case INDEX_op_brcond_i32: > case INDEX_op_brcond_i64: > return C_O0_I2(rZ, rZ);
On Wed, May 3, 2023 at 6:57 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target-con-set.h | 1 + > tcg/riscv/tcg-target.h | 8 ++++---- > tcg/riscv/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++ > 3 files changed, 40 insertions(+), 4 deletions(-) > > diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h > index a5cadd303f..aac5ceee2b 100644 > --- a/tcg/riscv/tcg-target-con-set.h > +++ b/tcg/riscv/tcg-target-con-set.h > @@ -18,5 +18,6 @@ C_O1_I2(r, r, rI) > C_O1_I2(r, r, rJ) > C_O1_I2(r, rZ, rN) > C_O1_I2(r, rZ, rZ) > +C_N1_I2(r, r, rM) > C_O1_I4(r, r, rI, rM, rM) > C_O2_I4(r, r, rZ, rZ, rM, rM) > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index e9e84be9a5..cff5de5c9e 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -125,8 +125,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_eqv_i32 have_zbb > #define TCG_TARGET_HAS_nand_i32 0 > #define TCG_TARGET_HAS_nor_i32 0 > -#define TCG_TARGET_HAS_clz_i32 0 > -#define TCG_TARGET_HAS_ctz_i32 0 > +#define TCG_TARGET_HAS_clz_i32 1 > +#define TCG_TARGET_HAS_ctz_i32 1 > #define TCG_TARGET_HAS_ctpop_i32 have_zbb > #define TCG_TARGET_HAS_brcond2 1 > #define TCG_TARGET_HAS_setcond2 1 > @@ -159,8 +159,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_eqv_i64 have_zbb > #define TCG_TARGET_HAS_nand_i64 0 > #define TCG_TARGET_HAS_nor_i64 0 > -#define TCG_TARGET_HAS_clz_i64 0 > -#define TCG_TARGET_HAS_ctz_i64 0 > +#define TCG_TARGET_HAS_clz_i64 1 > +#define TCG_TARGET_HAS_ctz_i64 1 > #define TCG_TARGET_HAS_ctpop_i64 have_zbb > #define TCG_TARGET_HAS_add2_i64 1 > #define TCG_TARGET_HAS_sub2_i64 1 > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 1c57b64182..a1c92b0603 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1063,6 +1063,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, > } > } > > +static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, > + TCGReg ret, TCGReg src1, int src2, bool c_src2) > +{ > + tcg_out_opc_imm(s, insn, ret, src1, 0); > + > + if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { > + /* > + * The requested zero result does not match the insn, so adjust. > + * Note that constraints put 'ret' in a new register, so the > + * computation above did not clobber either 'src1' or 'src2'. > + */ > + tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true, > + src2, c_src2, ret, false); > + } > +} > + > static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) > { > TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; > @@ -1724,6 +1740,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); > break; > > + case INDEX_op_clz_i32: > + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2); > + break; > + case INDEX_op_clz_i64: > + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2); > + break; > + case INDEX_op_ctz_i32: > + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2); > + break; > + case INDEX_op_ctz_i64: > + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2); > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1917,6 +1946,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_rotr_i64: > return C_O1_I2(r, r, ri); > > + case INDEX_op_clz_i32: > + case INDEX_op_clz_i64: > + case INDEX_op_ctz_i32: > + case INDEX_op_ctz_i64: > + return C_N1_I2(r, r, rM); > + > case INDEX_op_brcond_i32: > case INDEX_op_brcond_i64: > return C_O0_I2(rZ, rZ); > -- > 2.34.1 > >
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index a5cadd303f..aac5ceee2b 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -18,5 +18,6 @@ C_O1_I2(r, r, rI) C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) +C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e9e84be9a5..cff5de5c9e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -125,8 +125,8 @@ extern bool have_zbb; #define TCG_TARGET_HAS_eqv_i32 have_zbb #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 have_zbb #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 @@ -159,8 +159,8 @@ extern bool have_zbb; #define TCG_TARGET_HAS_eqv_i64 have_zbb #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 have_zbb #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1c57b64182..a1c92b0603 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1063,6 +1063,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, } } +static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, + TCGReg ret, TCGReg src1, int src2, bool c_src2) +{ + tcg_out_opc_imm(s, insn, ret, src1, 0); + + if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { + /* + * The requested zero result does not match the insn, so adjust. + * Note that constraints put 'ret' in a new register, so the + * computation above did not clobber either 'src1' or 'src2'. + */ + tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true, + src2, c_src2, ret, false); + } +} + static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; @@ -1724,6 +1740,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); break; + case INDEX_op_clz_i32: + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2); + break; + case INDEX_op_clz_i64: + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2); + break; + case INDEX_op_ctz_i32: + tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2); + break; + case INDEX_op_ctz_i64: + tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2); + break; + case INDEX_op_add2_i32: tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], const_args[4], const_args[5], false, true); @@ -1917,6 +1946,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotr_i64: return C_O1_I2(r, r, ri); + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: + return C_N1_I2(r, r, rM); + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.h | 8 ++++---- tcg/riscv/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 4 deletions(-)