| Message ID | 20230503085657.1814850-9-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand |
On 5/3/23 05:56, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > tcg/riscv/tcg-target.h | 4 ++-- > tcg/riscv/tcg-target.c.inc | 9 +++++++++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 8e327afc3a..e0b23006c4 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -127,7 +127,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_nor_i32 0 > #define TCG_TARGET_HAS_clz_i32 0 > #define TCG_TARGET_HAS_ctz_i32 0 > -#define TCG_TARGET_HAS_ctpop_i32 0 > +#define TCG_TARGET_HAS_ctpop_i32 have_zbb > #define TCG_TARGET_HAS_brcond2 1 > #define TCG_TARGET_HAS_setcond2 1 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > @@ -161,7 +161,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_nor_i64 0 > #define TCG_TARGET_HAS_clz_i64 0 > #define TCG_TARGET_HAS_ctz_i64 0 > -#define TCG_TARGET_HAS_ctpop_i64 0 > +#define TCG_TARGET_HAS_ctpop_i64 have_zbb > #define TCG_TARGET_HAS_add2_i64 1 > #define TCG_TARGET_HAS_sub2_i64 1 > #define TCG_TARGET_HAS_mulu2_i64 0 > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 9cbefb2833..044ddfb160 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1512,6 +1512,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + case INDEX_op_ctpop_i32: > + tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0); > + break; > + case INDEX_op_ctpop_i64: > + tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1634,6 +1641,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_bswap16_i64: > case INDEX_op_bswap32_i64: > case INDEX_op_bswap64_i64: > + case INDEX_op_ctpop_i32: > + case INDEX_op_ctpop_i64: > return C_O1_I1(r, r); > > case INDEX_op_st8_i32:
On Wed, May 3, 2023 at 6:58 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target.h | 4 ++-- > tcg/riscv/tcg-target.c.inc | 9 +++++++++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 8e327afc3a..e0b23006c4 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -127,7 +127,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_nor_i32 0 > #define TCG_TARGET_HAS_clz_i32 0 > #define TCG_TARGET_HAS_ctz_i32 0 > -#define TCG_TARGET_HAS_ctpop_i32 0 > +#define TCG_TARGET_HAS_ctpop_i32 have_zbb > #define TCG_TARGET_HAS_brcond2 1 > #define TCG_TARGET_HAS_setcond2 1 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > @@ -161,7 +161,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_nor_i64 0 > #define TCG_TARGET_HAS_clz_i64 0 > #define TCG_TARGET_HAS_ctz_i64 0 > -#define TCG_TARGET_HAS_ctpop_i64 0 > +#define TCG_TARGET_HAS_ctpop_i64 have_zbb > #define TCG_TARGET_HAS_add2_i64 1 > #define TCG_TARGET_HAS_sub2_i64 1 > #define TCG_TARGET_HAS_mulu2_i64 0 > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 9cbefb2833..044ddfb160 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1512,6 +1512,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + case INDEX_op_ctpop_i32: > + tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0); > + break; > + case INDEX_op_ctpop_i64: > + tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1634,6 +1641,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_bswap16_i64: > case INDEX_op_bswap32_i64: > case INDEX_op_bswap64_i64: > + case INDEX_op_ctpop_i32: > + case INDEX_op_ctpop_i64: > return C_O1_I1(r, r); > > case INDEX_op_st8_i32: > -- > 2.34.1 > >
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 8e327afc3a..e0b23006c4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -127,7 +127,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_ctpop_i32 have_zbb #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 @@ -161,7 +161,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_ctpop_i64 have_zbb #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9cbefb2833..044ddfb160 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1512,6 +1512,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_ctpop_i32: + tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0); + break; + case INDEX_op_ctpop_i64: + tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); + break; + case INDEX_op_add2_i32: tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], const_args[4], const_args[5], false, true); @@ -1634,6 +1641,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap16_i64: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-)