| Message ID | 20230503085657.1814850-8-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand |
On 5/3/23 05:56, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > tcg/riscv/tcg-target.h | 10 +++++----- > tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ > 2 files changed, 34 insertions(+), 5 deletions(-) > > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 317d385924..8e327afc3a 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -116,8 +116,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_ext16s_i32 1 > #define TCG_TARGET_HAS_ext8u_i32 1 > #define TCG_TARGET_HAS_ext16u_i32 1 > -#define TCG_TARGET_HAS_bswap16_i32 0 > -#define TCG_TARGET_HAS_bswap32_i32 0 > +#define TCG_TARGET_HAS_bswap16_i32 have_zbb > +#define TCG_TARGET_HAS_bswap32_i32 have_zbb > #define TCG_TARGET_HAS_not_i32 1 > #define TCG_TARGET_HAS_neg_i32 1 > #define TCG_TARGET_HAS_andc_i32 have_zbb > @@ -149,9 +149,9 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_ext8u_i64 1 > #define TCG_TARGET_HAS_ext16u_i64 1 > #define TCG_TARGET_HAS_ext32u_i64 1 > -#define TCG_TARGET_HAS_bswap16_i64 0 > -#define TCG_TARGET_HAS_bswap32_i64 0 > -#define TCG_TARGET_HAS_bswap64_i64 0 > +#define TCG_TARGET_HAS_bswap16_i64 have_zbb > +#define TCG_TARGET_HAS_bswap32_i64 have_zbb > +#define TCG_TARGET_HAS_bswap64_i64 have_zbb > #define TCG_TARGET_HAS_not_i64 1 > #define TCG_TARGET_HAS_neg_i64 1 > #define TCG_TARGET_HAS_andc_i64 have_zbb > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 58f969b4fe..9cbefb2833 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1488,6 +1488,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + case INDEX_op_bswap64_i64: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + break; > + case INDEX_op_bswap32_i32: > + a2 = 0; > + /* fall through */ > + case INDEX_op_bswap32_i64: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + if (a2 & TCG_BSWAP_OZ) { > + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); > + } else { > + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); > + } > + break; > + case INDEX_op_bswap16_i64: > + case INDEX_op_bswap16_i32: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + if (a2 & TCG_BSWAP_OZ) { > + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); > + } else { > + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); > + } > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1605,6 +1629,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > case INDEX_op_ext_i32_i64: > + case INDEX_op_bswap16_i32: > + case INDEX_op_bswap32_i32: > + case INDEX_op_bswap16_i64: > + case INDEX_op_bswap32_i64: > + case INDEX_op_bswap64_i64: > return C_O1_I1(r, r); > > case INDEX_op_st8_i32:
On Wed, May 3, 2023 at 6:59 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target.h | 10 +++++----- > tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ > 2 files changed, 34 insertions(+), 5 deletions(-) > > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 317d385924..8e327afc3a 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -116,8 +116,8 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_ext16s_i32 1 > #define TCG_TARGET_HAS_ext8u_i32 1 > #define TCG_TARGET_HAS_ext16u_i32 1 > -#define TCG_TARGET_HAS_bswap16_i32 0 > -#define TCG_TARGET_HAS_bswap32_i32 0 > +#define TCG_TARGET_HAS_bswap16_i32 have_zbb > +#define TCG_TARGET_HAS_bswap32_i32 have_zbb > #define TCG_TARGET_HAS_not_i32 1 > #define TCG_TARGET_HAS_neg_i32 1 > #define TCG_TARGET_HAS_andc_i32 have_zbb > @@ -149,9 +149,9 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_ext8u_i64 1 > #define TCG_TARGET_HAS_ext16u_i64 1 > #define TCG_TARGET_HAS_ext32u_i64 1 > -#define TCG_TARGET_HAS_bswap16_i64 0 > -#define TCG_TARGET_HAS_bswap32_i64 0 > -#define TCG_TARGET_HAS_bswap64_i64 0 > +#define TCG_TARGET_HAS_bswap16_i64 have_zbb > +#define TCG_TARGET_HAS_bswap32_i64 have_zbb > +#define TCG_TARGET_HAS_bswap64_i64 have_zbb > #define TCG_TARGET_HAS_not_i64 1 > #define TCG_TARGET_HAS_neg_i64 1 > #define TCG_TARGET_HAS_andc_i64 have_zbb > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 58f969b4fe..9cbefb2833 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1488,6 +1488,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + case INDEX_op_bswap64_i64: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + break; > + case INDEX_op_bswap32_i32: > + a2 = 0; > + /* fall through */ > + case INDEX_op_bswap32_i64: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + if (a2 & TCG_BSWAP_OZ) { > + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); > + } else { > + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); > + } > + break; > + case INDEX_op_bswap16_i64: > + case INDEX_op_bswap16_i32: > + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); > + if (a2 & TCG_BSWAP_OZ) { > + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); > + } else { > + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); > + } > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1605,6 +1629,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > case INDEX_op_ext_i32_i64: > + case INDEX_op_bswap16_i32: > + case INDEX_op_bswap32_i32: > + case INDEX_op_bswap16_i64: > + case INDEX_op_bswap32_i64: > + case INDEX_op_bswap64_i64: > return C_O1_I1(r, r); > > case INDEX_op_st8_i32: > -- > 2.34.1 > >
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 317d385924..8e327afc3a 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -116,8 +116,8 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_bswap16_i32 0 -#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 have_zbb +#define TCG_TARGET_HAS_bswap32_i32 have_zbb #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 have_zbb @@ -149,9 +149,9 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_bswap16_i64 0 -#define TCG_TARGET_HAS_bswap32_i64 0 -#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 have_zbb +#define TCG_TARGET_HAS_bswap32_i64 have_zbb +#define TCG_TARGET_HAS_bswap64_i64 have_zbb #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 have_zbb diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 58f969b4fe..9cbefb2833 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1488,6 +1488,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_bswap64_i64: + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); + break; + case INDEX_op_bswap32_i32: + a2 = 0; + /* fall through */ + case INDEX_op_bswap32_i64: + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); + if (a2 & TCG_BSWAP_OZ) { + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); + } else { + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); + } + break; + case INDEX_op_bswap16_i64: + case INDEX_op_bswap16_i32: + tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); + if (a2 & TCG_BSWAP_OZ) { + tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); + } else { + tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); + } + break; + case INDEX_op_add2_i32: tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], const_args[4], const_args[5], false, true); @@ -1605,6 +1629,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target.h | 10 +++++----- tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 5 deletions(-)