| Message ID | 1681468167-11689-1-git-send-email-quic_srichara@quicinc.com |
|---|---|
| Headers | show |
| Series | Add minimal boot support for IPQ5018 | expand |
On 14/04/2023 12:29, Sricharan Ramabadhran wrote: > Add device tree binding Documentation details for ipq5018 > pinctrl driver. > Thank you for your patch. There is something to discuss/improve. > + > + interrupt-controller: true > + "#interrupt-cells": true > + gpio-controller: true > + "#gpio-cells": true > + gpio-ranges: true > + wakeup-parent: true > + > + gpio-reserved-ranges: > + minItems: 1 > + maxItems: 33 24 (you cannot have more than 24...) > + > + gpio-line-names: > + maxItems: 47 > + > +patternProperties: > + "-state$": > + oneOf: > + - $ref: "#/$defs/qcom-ipq5018-tlmm-state" > + - patternProperties: > + "-pins$": > + $ref: "#/$defs/qcom-ipq5018-tlmm-state" > + additionalProperties: false > + > +$defs: > + qcom-ipq5018-tlmm-state: > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$" > + minItems: 1 > + maxItems: 8 > + > + function: > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd, > + audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd, > + audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0, > + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, > + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, > + blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng, > + cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio, > + gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio, > + pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test, > + prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, > + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, > + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, > + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, > + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, > + qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs, > + qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd, > + wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ] > + > + bias-pull-down: true > + bias-pull-up: true > + bias-disable: true > + drive-strength: true > + input-enable: true > + output-high: true > + output-low: true Drop all these 7, especially that input-enable is not allowed explicitly. > + > + required: > + - pins > + > + additionalProperties: false Instead: unevaluatedProperties: false and put it after the $ref above. Just like recent changes in the next. > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + tlmm: pinctrl@1000000 { > + compatible = "qcom,ipq5018-tlmm"; > + reg = <0x01000000 0x300000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&tlmm 0 0 47>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + uart2-state { > + pins = "gpio34", "gpio35"; > + function = "blsp2_uart"; Does not look like you tested the bindings. Please run `make dt_binding_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). Best regards, Krzysztof
On 14/04/2023 12:29, Sricharan Ramabadhran wrote: > The IPQ5018 is Qualcomm's 802.11ax SoC for Routers, > Gateways and Access Points. > > This series adds minimal board boot support for ipq5018-mp03.1-c2 board. > > [v3] > Fixed all comments for clocks, schema fixes > Picked up Reviewed-by from Bjorn for pinctrl driver Didn't you just ignore all the tags you got? I was already acking and reviewing a lot of these... Best regards, Krzysztof
On 14/04/2023 12:29, Sricharan Ramabadhran wrote: > Document the compatible for SDHCI on IPQ5018. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> This is an automated instruction, just in case, because many review tags are being ignored. If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540 Best regards, Krzysztof
Hi Krysztof, On 4/16/2023 2:37 PM, Krzysztof Kozlowski wrote: > On 14/04/2023 12:29, Sricharan Ramabadhran wrote: >> The IPQ5018 is Qualcomm's 802.11ax SoC for Routers, >> Gateways and Access Points. >> >> This series adds minimal board boot support for ipq5018-mp03.1-c2 board. >> >> [v3] >> Fixed all comments for clocks, schema fixes >> Picked up Reviewed-by from Bjorn for pinctrl driver > > Didn't you just ignore all the tags you got? I was already acking and > reviewing a lot of these... > While i got review comments for V2, only one tag from Bjorn (reviewed-by) for the pinctrl driver. That one i picked. Regards, Sricharan
On 4/16/2023 2:35 PM, Krzysztof Kozlowski wrote: > On 14/04/2023 12:29, Sricharan Ramabadhran wrote: >> Add device tree binding Documentation details for ipq5018 >> pinctrl driver. >> > > Thank you for your patch. There is something to discuss/improve. > >> + >> + interrupt-controller: true >> + "#interrupt-cells": true >> + gpio-controller: true >> + "#gpio-cells": true >> + gpio-ranges: true >> + wakeup-parent: true >> + >> + gpio-reserved-ranges: >> + minItems: 1 >> + maxItems: 33 > > 24 > (you cannot have more than 24...) > ok, will change this. >> + >> + gpio-line-names: >> + maxItems: 47 >> + >> +patternProperties: >> + "-state$": >> + oneOf: >> + - $ref: "#/$defs/qcom-ipq5018-tlmm-state" >> + - patternProperties: >> + "-pins$": >> + $ref: "#/$defs/qcom-ipq5018-tlmm-state" >> + additionalProperties: false >> + >> +$defs: >> + qcom-ipq5018-tlmm-state: >> + type: object >> + description: >> + Pinctrl node's client devices use subnodes for desired pin configuration. >> + Client device subnodes use below standard properties. >> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state >> + >> + properties: >> + pins: >> + description: >> + List of gpio pins affected by the properties specified in this >> + subnode. >> + items: >> + pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$" >> + minItems: 1 >> + maxItems: 8 >> + >> + function: >> + description: >> + Specify the alternative function to be configured for the specified >> + pins. >> + >> + enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd, >> + audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd, >> + audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0, >> + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, >> + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, >> + blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng, >> + cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio, >> + gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio, >> + pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test, >> + prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, >> + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, >> + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, >> + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, >> + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, >> + qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs, >> + qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd, >> + wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ] >> + >> + bias-pull-down: true >> + bias-pull-up: true >> + bias-disable: true >> + drive-strength: true >> + input-enable: true >> + output-high: true >> + output-low: true > > Drop all these 7, especially that input-enable is not allowed explicitly. > ok. >> + >> + required: >> + - pins >> + >> + additionalProperties: false > > Instead: > unevaluatedProperties: false > and put it after the $ref above. Just like recent changes in the next. > ok, will check and fix it. >> + >> +required: >> + - compatible >> + - reg >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + tlmm: pinctrl@1000000 { >> + compatible = "qcom,ipq5018-tlmm"; >> + reg = <0x01000000 0x300000>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 47>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + >> + uart2-state { >> + pins = "gpio34", "gpio35"; >> + function = "blsp2_uart"; > > Does not look like you tested the bindings. Please run `make > dt_binding_check` (see > Documentation/devicetree/bindings/writing-schema.rst for instructions). I ran it against the TOT, will run it this time on nxt and post V4. Regards, Sricharan
On 17/04/2023 08:13, Sricharan Ramabadhran wrote: >>> + tlmm: pinctrl@1000000 { >>> + compatible = "qcom,ipq5018-tlmm"; >>> + reg = <0x01000000 0x300000>; >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + gpio-ranges = <&tlmm 0 0 47>; >>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + >>> + uart2-state { >>> + pins = "gpio34", "gpio35"; >>> + function = "blsp2_uart"; >> >> Does not look like you tested the bindings. Please run `make >> dt_binding_check` (see >> Documentation/devicetree/bindings/writing-schema.rst for instructions). > > I ran it against the TOT, will run it this time on nxt and post V4. I don't know what is TOT, but this would fail in every case on every tree. Best regards, Krzysztof
On Fri, 14 Apr 2023 at 12:35, Sricharan Ramabadhran <quic_srichara@quicinc.com> wrote: > > Document the compatible for SDHCI on IPQ5018. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > index 7d4c5ca..4f2d9e8 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > @@ -34,6 +34,7 @@ properties: > - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 > - items: > - enum: > + - qcom,ipq5018-sdhci > - qcom,ipq5332-sdhci > - qcom,ipq9574-sdhci > - qcom,qcm2290-sdhci > -- > 2.7.4 >
The IPQ5018 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq5018-mp03.1-c2 board. [v3] Fixed all comments for clocks, schema fixes Picked up Reviewed-by from Bjorn for pinctrl driver [v2] Fixed all comments and rebased for TOT. Sricharan Ramabadhran (9): dt-bindings: arm64: Add IPQ5018 clock and reset clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 dt-bindings: pinctrl: qcom: Add support for ipq5018 pinctrl: qcom: Add IPQ5018 pinctrl driver dt-bindings: qcom: Add ipq5018 bindings dt-bindings: firmware: document IPQ5018 SCM dt-bindings: mmc: sdhci-msm: Document the IPQ5018 compatible arm64: dts: Add ipq5018 SoC and rdp432-c2 board support arm64: defconfig: Enable IPQ5018 SoC base configs Documentation/devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,ipq5018-gcc.yaml | 63 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + .../devicetree/bindings/mmc/sdhci-msm.yaml | 1 + .../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 129 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 248 ++ arch/arm64/configs/defconfig | 3 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5018.c | 3731 ++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5018.c | 791 +++++ include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 + include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 + 17 files changed, 5371 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq5018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h