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[v2,51/54] tcg/ppc: Remove unused constraints A, B, C, D

Message ID	20230411010512.5375-52-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D Date: Mon, 10 Apr 2023 18:05:09 -0700 Message-Id: <20230411010512.5375-52-richard.henderson@linaro.org> In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Simplify calls to load/store helpers \| expand [v2,00/54] tcg: Simplify calls to load/store helpers [v2,01/54] tcg: Replace if + tcg_abort with tcg_debug_assert [v2,02/54] tcg: Replace tcg_abort with g_assert_not_reached [v2,03/54] tcg: Split out tcg_out_ext8s [v2,04/54] tcg: Split out tcg_out_ext8u [v2,05/54] tcg: Split out tcg_out_ext16s [v2,06/54] tcg: Split out tcg_out_ext16u [v2,07/54] tcg: Split out tcg_out_ext32s [v2,08/54] tcg: Split out tcg_out_ext32u [v2,09/54] tcg: Split out tcg_out_exts_i32_i64 [v2,10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 [v2,11/54] tcg/mips: Conditionalize tcg_out_exts_i32_i64 [v2,12/54] tcg/riscv: Conditionalize tcg_out_exts_i32_i64 [v2,13/54] tcg: Split out tcg_out_extu_i32_i64 [v2,14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 [v2,15/54] tcg: Split out tcg_out_extrl_i64_i32 [v2,16/54] tcg: Introduce tcg_out_movext [v2,17/54] tcg: Introduce tcg_out_xchg [v2,18/54] tcg: Introduce tcg_out_movext2 [v2,19/54] tcg: Clear TCGLabelQemuLdst on allocation [v2,20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} [v2,21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} [v2,22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} [v2,23/54] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} [v2,24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} [v2,25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} [v2,26/54] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} [v2,27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 [v2,28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} [v2,29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return [v2,30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} [v2,31/54] tcg: Move TCGLabelQemuLdst to tcg.c [v2,32/54] tcg: Replace REG_P with arg_loc_reg_p [v2,33/54] tcg: Introduce arg_slot_stk_ofs [v2,34/54] tcg: Widen helper_*_st[bw]_mmu val arguments [v2,35/54] tcg: Add routines for calling slow-path helpers [v2,36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path [v2,37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path [v2,38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path [v2,39/54] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path [v2,40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path [v2,41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path [v2,42/54] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path [v2,43/54] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path [v2,44/54] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path [v2,45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st [v2,46/54] tcg/mips: Remove MO_BSWAP handling [v2,47/54] tcg/mips: Reorg tcg_out_tlb_load [v2,48/54] tcg/mips: Simplify constraints on qemu_ld/st [v2,49/54] tcg/ppc: Reorg tcg_out_tlb_read [v2,50/54] tcg/ppc: Adjust constraints on qemu_ld/st [v2,51/54] tcg/ppc: Remove unused constraints A, B, C, D [v2,52/54] tcg/riscv: Simplify constraints on qemu_ld/st [v2,53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st [v2,54/54] tcg/s390x: Simplify constraints on qemu_ld/st

Commit Message

Richard Henderson April 11, 2023, 1:05 a.m. UTC

These constraints have not been used for quite some time.

Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-str.h | 4 ----
 1 file changed, 4 deletions(-)

Comments

Daniel Henrique Barboza April 12, 2023, 7:09 p.m. UTC | #1

On 4/10/23 22:05, Richard Henderson wrote:
> These constraints have not been used for quite some time.
> 
> Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   tcg/ppc/tcg-target-con-str.h | 4 ----
>   1 file changed, 4 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
> index f3bf030bc3..9dcbc3df50 100644
> --- a/tcg/ppc/tcg-target-con-str.h
> +++ b/tcg/ppc/tcg-target-con-str.h
> @@ -10,10 +10,6 @@
>    */
>   REGS('r', ALL_GENERAL_REGS)
>   REGS('v', ALL_VECTOR_REGS)
> -REGS('A', 1u << TCG_REG_R3)
> -REGS('B', 1u << TCG_REG_R4)
> -REGS('C', 1u << TCG_REG_R5)
> -REGS('D', 1u << TCG_REG_R6)
>   
>   /*
>    * Define constraint letters for constants:

diff mbox series

Patch

diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
index f3bf030bc3..9dcbc3df50 100644
--- a/tcg/ppc/tcg-target-con-str.h
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -10,10 +10,6 @@ 
  */
 REGS('r', ALL_GENERAL_REGS)
 REGS('v', ALL_VECTOR_REGS)
-REGS('A', 1u << TCG_REG_R3)
-REGS('B', 1u << TCG_REG_R4)
-REGS('C', 1u << TCG_REG_R5)
-REGS('D', 1u << TCG_REG_R6)
 
 /*
  * Define constraint letters for constants: