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[v5,00/19] Qcom PCIe cleanups and improvements

Message ID 20230316081117.14288-1-manivannan.sadhasivam@linaro.org
Headers show
Series Qcom PCIe cleanups and improvements | expand

Message

Manivannan Sadhasivam March 16, 2023, 8:10 a.m. UTC 
Hi,

This series brings in several code cleanups and improvements to the
Qualcomm PCIe controller drivers (RC and EP). The cleanup part mostly
cleans up the bitfield definitions and transitions to bulk APIs for clocks,
and resets. The improvement part adds the debugfs entries to track link
transition counts in RC driver.

Testing
-------

This series has been tested on SDM845, SM8250, SC8280XP, IPQ4019 based
platforms.

Merging Strategy
----------------

Binding and driver patches through PCI tree and DTS patches through Qcom
tree.

NOTE: For the sake of maintaining dependency, I've clubbed both cleanup and
improvement patches in the same series. If any of the maintainers prefer to
have them splitted, please let me know.

Thanks,
Mani

Changes in v5:

* Added a new patch to fix an incorrect register usage in config v2.7.0
* Added Reviewed-by tag to the binding which got missed in v4.

Changes in v4:

* Dropped the debugfs patch for v2.4.0 as the registers only expose the status
  and not the transition count which is not useful
* Modified the existing debugfs patch to be applicable for all SoCs that define
  "mhi" region

Changes in v3:

* Introduced init_debugfs callback for defining the debugfs interface specific
  to IP versions
* Added a debugfs patch for v2.4.0
* Added a patch to rename qcom_pcie_config_sid_sm8250() function
* Added tested-by for patch 11/19

Changes in v2:

* Moved the "mhi" region to last in the binding and dtsi's
* Dropped the patches renaming the "mmio" region

Manivannan Sadhasivam (19):
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use lower case for hex
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
  PCI: qcom: Expose link transition counts via debugfs

 .../devicetree/bindings/pci/qcom,pcie.yaml    |   12 +-
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        |   25 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |   10 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |   15 +-
 drivers/pci/controller/dwc/pcie-qcom.c        | 1158 +++++++----------
 5 files changed, 476 insertions(+), 744 deletions(-)

Comments

Lorenzo Pieralisi April 11, 2023, 9:34 a.m. UTC | #1 
On Thu, 16 Mar 2023 13:40:58 +0530, Manivannan Sadhasivam wrote:
> This series brings in several code cleanups and improvements to the
> Qualcomm PCIe controller drivers (RC and EP). The cleanup part mostly
> cleans up the bitfield definitions and transitions to bulk APIs for clocks,
> and resets. The improvement part adds the debugfs entries to track link
> transition counts in RC driver.
> 
> Testing
> -------
> 
> [...]

Applied to controller/qcom, thanks!

[01/19] PCI: qcom: Fix the incorrect register usage in v2.7.0 config
        https://git.kernel.org/pci/pci/c/2542e16c3925
[02/19] PCI: qcom: Remove PCIE20_ prefix from register definitions
        https://git.kernel.org/pci/pci/c/39171b33f652
[03/19] PCI: qcom: Sort and group registers and bitfield definitions
        https://git.kernel.org/pci/pci/c/769e49d87b15
[04/19] PCI: qcom: Use bitfield definitions for register fields
        https://git.kernel.org/pci/pci/c/57eddec8dc30
[05/19] PCI: qcom: Add missing macros for register fields
        https://git.kernel.org/pci/pci/c/17804668ca54
[06/19] PCI: qcom: Use lower case for hex
        https://git.kernel.org/pci/pci/c/94ebd232dbc8
[07/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
        https://git.kernel.org/pci/pci/c/383215dd2fd7
[08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
        https://git.kernel.org/pci/pci/c/5d4ffe5ec5e9
[09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
        https://git.kernel.org/pci/pci/c/5329bcc4a1e7
[10/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
        https://git.kernel.org/pci/pci/c/b699ed9b03de
[11/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
        https://git.kernel.org/pci/pci/c/157fecca3558
[12/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
        https://git.kernel.org/pci/pci/c/fb0eacb2972e
[13/19] PCI: qcom: Use macros for defining total no. of clocks & supplies
        https://git.kernel.org/pci/pci/c/656a08820e7b
[14/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
        https://git.kernel.org/pci/pci/c/1f70939871b2
[15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
        https://git.kernel.org/pci/pci/c/0f80edf8447d
[19/19] PCI: qcom: Expose link transition counts via debugfs
        https://git.kernel.org/pci/pci/c/05f464640962

Thanks,
Lorenzo