| Message ID | cover.1679909245.git.quic_varada@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable IPQ9754 USB | expand |
On Tue, Mar 28, 2023 at 09:11:38AM +0200, Krzysztof Kozlowski wrote: > On 27/03/2023 11:30, Varadarajan Narayanan wrote: > > Document the IPQ9574 dwc3 compatible. > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > Changes in v4: > > - Update other relevant sections > > - Remove constraints not applicable to IPQ9574 > > No, that's not way to go. These are required. Yes. Misinterpreted an earlier comment. Will fix this. > > --- > > .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++--- > > 1 file changed, 19 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > index a2aabda..3fc8c3c 100644 > > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > @@ -17,6 +17,7 @@ properties: > > - qcom,ipq6018-dwc3 > > - qcom,ipq8064-dwc3 > > - qcom,ipq8074-dwc3 > > + - qcom,ipq9574-dwc3 > > - qcom,msm8953-dwc3 > > - qcom,msm8994-dwc3 > > - qcom,msm8996-dwc3 > > @@ -132,11 +133,8 @@ required: > > - "#address-cells" > > - "#size-cells" > > - ranges > > - - power-domains > > - clocks > > - clock-names > > - - interrupts > > - - interrupt-names > > > > allOf: > > - if: > > @@ -242,6 +240,24 @@ allOf: > > compatible: > > contains: > > enum: > > + - qcom,ipq9574-dwc3 > > + then: > > + properties: > > + clocks: > > + maxItems: 5 > > + clock-names: > > + items: > > + - const: sys_noc_axi > > + - const: anoc_axi > > Heh, do we really need entirely different clock names for each new variant? Will fix and post a new patch. Thanks Varada > Best regards, > Krzysztof >
On Tue, Mar 28, 2023 at 09:09:09AM +0200, Krzysztof Kozlowski wrote: > On 27/03/2023 11:30, Varadarajan Narayanan wrote: > > Add USB phy and controller related nodes > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > Changes in v4: > > - Use newer bindings without subnodes > > - Fix coding style issues > > > > Changes in v3: > > - Insert the nodes at proper location > > > > Changes in v2: > > - Fixed issues flagged by Krzysztof > > - Fix issues reported by make dtbs_check > > - Remove NOC related clocks (to be added with proper > > interconnect support) > > --- > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 83 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > index 2bb4053..5379c25 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > @@ -215,6 +215,45 @@ > > #size-cells = <1>; > > ranges = <0 0 0 0xffffffff>; > > > > + qusb_phy_0: phy@7b000 { > > + compatible = "qcom,ipq9574-qusb2-phy"; > > + reg = <0x0007b000 0x180>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&xo_board_clk>; > > + clock-names = "cfg_ahb", > > + "ref"; > > + > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > + status = "disabled"; > > + }; > > + > > + ssphy_0: phy@7d000 { > > + compatible = "qcom,ipq9574-qmp-usb3-phy"; > > + reg = <0x0007d000 0xa00>; > > + #clock-cells = <1>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > Why do you need these three? Don't need these. Have moved to qcom,sc8280xp-qmp-usb3-uni-phy.yaml specification instead of qcom,msm8996-qmp-usb3-phy.yaml. Will update accordingly and post. > > + > > + clocks = <&gcc GCC_USB0_AUX_CLK>, > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_USB0_PIPE_CLK>; > > + clock-names = "aux", > > + "cfg_ahb", > > + "pipe"; > > + > > + resets = <&gcc GCC_USB0_PHY_BCR>, > > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > > + reset-names = "phy", > > + "common"; > > + status = "disabled"; > > + > > + #phy-cells = <0>; > > + clock-output-names = "usb0_pipe_clk"; > > Does not look like you tested the DTS against bindings. Please run `make > dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst > for instructions). Have addressed these and have created a new patch. Will post it shortly. IPQ9574 doesn't have any power domains, hence don't have power-domains entry in the DT node. make dtbs_check is giving the following messages hope that is ok /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > > + }; > > + > > pcie0_phy: phy@84000 { > > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > > reg = <0x00084000 0x1bc>; /* Serdes PLL */ > > @@ -436,6 +475,50 @@ > > status = "disabled"; > > }; > > > > + usb3: usb3@8a00000 { > > usb@ Will fix. > > + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; > > + reg = <0x08af8800 0x400>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > > > > + > > + clocks = <&gcc GCC_SNOC_USB_CLK>, > > + <&gcc GCC_ANOC_USB_AXI_CLK>, > > + <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_SLEEP_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + > > + clock-names = "sys_noc_axi", > > + "anoc_axi", > > + "master", > > + "sleep", > > + "mock_utmi"; > > + > > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + assigned-clock-rates = <200000000>, > > + <24000000>; > > + > > + resets = <&gcc GCC_USB_BCR>; > > + status = "disabled"; > > + > > + dwc_0: usb@8a00000 { > > + compatible = "snps,dwc3"; > > + reg = <0x8a00000 0xcd00>; > > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + clock-names = "ref"; > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&qusb_phy_0>, <&ssphy_0>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + tx-fifo-resize; > > + snps,is-utmi-l1-suspend; > > + snps,hird-threshold = /bits/ 8 <0x0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > + dr_mode = "host"; > > Are you saying that peripheral mode cannot work on this USB controller? > Never? Will move to board DTS. Thanks Varada > Best regards, > Krzysztof >
This patch series adds the relevant phy and controller configurations for enabling USB on IPQ9754 Depends on: https://lore.kernel.org/all/20230217142030.16012-1-quic_devipriy@quicinc.com/ [v4]: - Incorporated review comments - Address all 'make dtbs_check' errors [v3]: - Incorporated review comments regarding coding style [v2]: - Incorporated review comments regarding coding style, maintaining sorted order of entries and unused phy register offsets - Removed NOC clock entries from DT node (will be implemented later with interconnect support) - Fixed 'make dtbs_check' errors/warnings [v1]: https://lore.kernel.org/linux-arm-msm/5dac3aa4-8dc7-f9eb-5cf3-b361efdc9494@linaro.org/T/ Varadarajan Narayanan (8): dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY dt-bindings: usb: dwc3: Add IPQ9574 compatible clk: qcom: gcc-ipq9574: Add USB related clocks phy: qcom-qusb2: add QUSB2 support for IPQ9574 phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence arm64: dts: qcom: ipq9574: Add USB related nodes arm64: dts: qcom: ipq9574: Enable USB .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 +++- .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 +- .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++- arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++ drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 + 9 files changed, 310 insertions(+), 9 deletions(-)