Message ID | 1679036039-27157-1-git-send-email-quic_rohiagar@quicinc.com |
---|---|
Headers | show |
Series | Add PCIe EP support for SDX65 | expand |
On Fri, Mar 17, 2023 at 12:23:55PM +0530, Rohit Agarwal wrote: > Add PCIe EP compatible string for SDX65 SoC. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 89cfdee..096540b 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -13,6 +13,7 @@ properties: > compatible: > enum: > - qcom,sdx55-pcie-ep > + - qcom,sdx65-pcie-ep > - qcom,sm8450-pcie-ep > > reg: > @@ -109,6 +110,7 @@ allOf: > contains: > enum: > - qcom,sdx55-pcie-ep > + - qcom,sdx65-pcie-ep > then: > properties: > clocks: > -- > 2.7.4 >
On 17.03.2023 07:53, Rohit Agarwal wrote: > Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is > used by the PCIe EP controller. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 192f9f9..084daf8 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -293,6 +293,37 @@ > status = "disabled"; > }; > > + pcie_phy: phy@1c06000 { > + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; > + reg = <0x01c06000 0x2000>; > + > + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_EN>, > + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, > + <&gcc GCC_PCIE_PIPE_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe"; > + > + resets = <&gcc GCC_PCIE_PHY_BCR>; > + reset-names = "phy"; > + > + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > + assigned-clock-rates = <100000000>; > + > + power-domains = <&gcc PCIE_GDSC>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x01f40000 0x40000>;
On 17.03.2023 07:53, Rohit Agarwal wrote: > Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it, > updating status as last property for each node. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm/boot/dts/qcom-sdx65-mtp.dts | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > index ed98c83..70720e6 100644 > --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts > +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > @@ -245,6 +245,13 @@ > status = "okay"; > }; > > +&pcie_phy { > + vdda-phy-supply = <&vreg_l1b_1p2>; > + vdda-pll-supply = <&vreg_l4b_0p88>; > + > + status = "okay"; > +}; > + > &qpic_bam { > status = "okay"; > }; > @@ -265,8 +272,9 @@ > }; > > &remoteproc_mpss { > - status = "okay"; > memory-region = <&mpss_adsp_mem>; > + > + status = "okay"; > }; > > &usb { > @@ -278,14 +286,16 @@ > }; > > &usb_hsphy { > - status = "okay"; > vdda-pll-supply = <&vreg_l4b_0p88>; > vdda33-supply = <&vreg_l10b_3p08>; > vdda18-supply = <&vreg_l5b_1p8>; > + > + status = "okay"; > }; > > &usb_qmpphy { > - status = "okay"; > vdda-phy-supply = <&vreg_l4b_0p88>; > vdda-pll-supply = <&vreg_l1b_1p2>; > + > + status = "okay"; > };