| Message ID | 20221209-dt-binding-ufs-v3-3-499dff23a03c@fairphone.com |
|---|---|
| State | New |
| Headers | show |
| Series | Fix some issues in QCOM UFS bindings | expand |
On Fri, Mar 24, 2023 at 08:41:30AM +0100, Luca Weiss wrote: > SM8450 actually supports ICE (Inline Crypto Engine) so adjust the > bindings and the example to match. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index ebc8e1adbc6f..3af786120fa5 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -113,7 +113,6 @@ allOf: > - qcom,sc8280xp-ufshc > - qcom,sm8250-ufshc > - qcom,sm8350-ufshc > - - qcom,sm8450-ufshc > - qcom,sm8550-ufshc > then: > properties: > @@ -144,6 +143,7 @@ allOf: > - qcom,sdm845-ufshc > - qcom,sm6350-ufshc > - qcom,sm8150-ufshc > + - qcom,sm8450-ufshc > then: > properties: > clocks: > @@ -250,7 +250,9 @@ examples: > ufs@1d84000 { > compatible = "qcom,sm8450-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > - reg = <0 0x01d84000 0 0x3000>; > + reg = <0 0x01d84000 0 0x3000>, > + <0 0x01d88000 0 0x8000>; > + reg-names = "std", "ice"; > interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > phys = <&ufs_mem_phy_lanes>; > phy-names = "ufsphy"; > @@ -278,7 +280,8 @@ examples: > "ref_clk", > "tx_lane0_sync_clk", > "rx_lane0_sync_clk", > - "rx_lane1_sync_clk"; > + "rx_lane1_sync_clk", > + "ice_core_clk"; > clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > <&gcc GCC_UFS_PHY_AHB_CLK>, > @@ -286,7 +289,8 @@ examples: > <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, > + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > freq-table-hz = <75000000 300000000>, > <0 0>, > <0 0>, > @@ -294,6 +298,7 @@ examples: > <75000000 300000000>, > <0 0>, > <0 0>, > - <0 0>; > + <0 0>, > + <75000000 300000000>; > }; Reviewed-by: Eric Biggers <ebiggers@google.com> - Eric
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index ebc8e1adbc6f..3af786120fa5 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -113,7 +113,6 @@ allOf: - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - qcom,sm8550-ufshc then: properties: @@ -144,6 +143,7 @@ allOf: - qcom,sdm845-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc + - qcom,sm8450-ufshc then: properties: clocks: @@ -250,7 +250,9 @@ examples: ufs@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; + reg = <0 0x01d84000 0 0x3000>, + <0 0x01d88000 0 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -278,7 +280,8 @@ examples: "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -286,7 +289,8 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, <0 0>, @@ -294,6 +298,7 @@ examples: <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; }; };