| Message ID | 20230307153201.180626-1-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Accepted |
| Commit | e607b3c1fa0e1579951acd00f9559a77f97d0927 |
| Headers | show |
| Series | [1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent | expand |
On Tue, 7 Mar 2023 21:02:00 +0530, Manivannan Sadhasivam wrote: > The UFS controller on SM8350 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Applied, thanks! [1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent commit: e607b3c1fa0e1579951acd00f9559a77f97d0927 [2/2] arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent commit: 8ba961d4339c5db0e69ff6627606fe1f34c838e5 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..1a5a612d4234 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1664,6 +1664,7 @@ ufs_mem_hc: ufshc@1d84000 { power-domains = <&gcc UFS_PHY_GDSC>; iommus = <&apps_smmu 0xe0 0x0>; + dma-coherent; clock-names = "core_clk",
The UFS controller on SM8350 supports cache coherency, hence add the "dma-coherent" property to mark it as such. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+)