[52/76] target/riscv: Drop temp_new

Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/translate.c                  | 30 +++++------------------
 target/riscv/insn_trans/trans_rvzfh.c.inc |  2 +-
 2 files changed, 7 insertions(+), 25 deletions(-)

On 2/25/23 06:14, Richard Henderson wrote:
> Translators are no longer required to free tcg temporaries,
> therefore there's no need to record temps for later freeing.
> Replace the few uses with tcg_temp_new.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/translate.c                  | 30 +++++------------------
>   target/riscv/insn_trans/trans_rvzfh.c.inc |  2 +-
>   2 files changed, 7 insertions(+), 25 deletions(-)
> 
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 273e566d66..b5d8080a6f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -101,11 +101,8 @@ typedef struct DisasContext {
>       bool cfg_vta_all_1s;
>       target_ulong vstart;
>       bool vl_eq_vlmax;
> -    uint8_t ntemp;
>       CPUState *cs;
>       TCGv zero;
> -    /* Space for 3 operands plus 1 extra for address computation. */
> -    TCGv temp[4];
>       /* PointerMasking extension */
>       bool pm_mask_enabled;
>       bool pm_base_enabled;
> @@ -312,12 +309,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
>    *
>    * Further, we may provide an extension for word operations.
>    */
> -static TCGv temp_new(DisasContext *ctx)
> -{
> -    assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> -    return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> -}
> -
>   static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
>   {
>       TCGv t;
> @@ -332,11 +323,11 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
>           case EXT_NONE:
>               break;
>           case EXT_SIGN:
> -            t = temp_new(ctx);
> +            t = tcg_temp_new();
>               tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
>               return t;
>           case EXT_ZERO:
> -            t = temp_new(ctx);
> +            t = tcg_temp_new();
>               tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
>               return t;
>           default:
> @@ -364,7 +355,7 @@ static TCGv get_gprh(DisasContext *ctx, int reg_num)
>   static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>   {
>       if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
> -        return temp_new(ctx);
> +        return tcg_temp_new();
>       }
>       return cpu_gpr[reg_num];
>   }
> @@ -372,7 +363,7 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>   static TCGv dest_gprh(DisasContext *ctx, int reg_num)
>   {
>       if (reg_num == 0) {
> -        return temp_new(ctx);
> +        return tcg_temp_new();
>       }
>       return cpu_gprh[reg_num];
>   }
> @@ -575,7 +566,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>   /* Compute a canonical address from a register plus offset. */
>   static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>   {
> -    TCGv addr = temp_new(ctx);
> +    TCGv addr = tcg_temp_new();
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_addi_tl(addr, src1, imm);
> @@ -593,7 +584,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>   /* Compute a canonical address from a register plus reg offset. */
>   static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
>   {
> -    TCGv addr = temp_new(ctx);
> +    TCGv addr = tcg_temp_new();
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_add_tl(addr, src1, offs);
> @@ -1196,8 +1187,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>       ctx->misa_mxl_max = env->misa_mxl_max;
>       ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
>       ctx->cs = cs;
> -    ctx->ntemp = 0;
> -    memset(ctx->temp, 0, sizeof(ctx->temp));
>       ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
>       ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
>       ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> @@ -1222,18 +1211,11 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>       DisasContext *ctx = container_of(dcbase, DisasContext, base);
>       CPURISCVState *env = cpu->env_ptr;
>       uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
> -    int i;
>   
>       ctx->ol = ctx->xl;
>       decode_opc(env, ctx, opcode16);
>       ctx->base.pc_next = ctx->pc_succ_insn;
>   
> -    for (i = ctx->ntemp - 1; i >= 0; --i) {
> -        tcg_temp_free(ctx->temp[i]);
> -        ctx->temp[i] = NULL;
> -    }
> -    ctx->ntemp = 0;
> -
>       /* Only the first insn within a TB is allowed to cross a page boundary. */
>       if (ctx->base.is_jmp == DISAS_NEXT) {
>           if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 2ad5716312..5024e6ecab 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -52,7 +52,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
>       decode_save_opc(ctx);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
>       if (a->imm) {
> -        TCGv temp = temp_new(ctx);
> +        TCGv temp = tcg_temp_new();
>           tcg_gen_addi_tl(temp, t0, a->imm);
>           t0 = temp;
>       }

On 2023/2/25 17:14, Richard Henderson wrote:
> Translators are no longer required to free tcg temporaries,
> therefore there's no need to record temps for later freeing.
> Replace the few uses with tcg_temp_new.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Oh. It's here.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li

> ---
>   target/riscv/translate.c                  | 30 +++++------------------
>   target/riscv/insn_trans/trans_rvzfh.c.inc |  2 +-
>   2 files changed, 7 insertions(+), 25 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 273e566d66..b5d8080a6f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -101,11 +101,8 @@ typedef struct DisasContext {
>       bool cfg_vta_all_1s;
>       target_ulong vstart;
>       bool vl_eq_vlmax;
> -    uint8_t ntemp;
>       CPUState *cs;
>       TCGv zero;
> -    /* Space for 3 operands plus 1 extra for address computation. */
> -    TCGv temp[4];
>       /* PointerMasking extension */
>       bool pm_mask_enabled;
>       bool pm_base_enabled;
> @@ -312,12 +309,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
>    *
>    * Further, we may provide an extension for word operations.
>    */
> -static TCGv temp_new(DisasContext *ctx)
> -{
> -    assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
> -    return ctx->temp[ctx->ntemp++] = tcg_temp_new();
> -}
> -
>   static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
>   {
>       TCGv t;
> @@ -332,11 +323,11 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
>           case EXT_NONE:
>               break;
>           case EXT_SIGN:
> -            t = temp_new(ctx);
> +            t = tcg_temp_new();
>               tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
>               return t;
>           case EXT_ZERO:
> -            t = temp_new(ctx);
> +            t = tcg_temp_new();
>               tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
>               return t;
>           default:
> @@ -364,7 +355,7 @@ static TCGv get_gprh(DisasContext *ctx, int reg_num)
>   static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>   {
>       if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
> -        return temp_new(ctx);
> +        return tcg_temp_new();
>       }
>       return cpu_gpr[reg_num];
>   }
> @@ -372,7 +363,7 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>   static TCGv dest_gprh(DisasContext *ctx, int reg_num)
>   {
>       if (reg_num == 0) {
> -        return temp_new(ctx);
> +        return tcg_temp_new();
>       }
>       return cpu_gprh[reg_num];
>   }
> @@ -575,7 +566,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>   /* Compute a canonical address from a register plus offset. */
>   static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>   {
> -    TCGv addr = temp_new(ctx);
> +    TCGv addr = tcg_temp_new();
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_addi_tl(addr, src1, imm);
> @@ -593,7 +584,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>   /* Compute a canonical address from a register plus reg offset. */
>   static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
>   {
> -    TCGv addr = temp_new(ctx);
> +    TCGv addr = tcg_temp_new();
>       TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>   
>       tcg_gen_add_tl(addr, src1, offs);
> @@ -1196,8 +1187,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>       ctx->misa_mxl_max = env->misa_mxl_max;
>       ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
>       ctx->cs = cs;
> -    ctx->ntemp = 0;
> -    memset(ctx->temp, 0, sizeof(ctx->temp));
>       ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
>       ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
>       ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> @@ -1222,18 +1211,11 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>       DisasContext *ctx = container_of(dcbase, DisasContext, base);
>       CPURISCVState *env = cpu->env_ptr;
>       uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
> -    int i;
>   
>       ctx->ol = ctx->xl;
>       decode_opc(env, ctx, opcode16);
>       ctx->base.pc_next = ctx->pc_succ_insn;
>   
> -    for (i = ctx->ntemp - 1; i >= 0; --i) {
> -        tcg_temp_free(ctx->temp[i]);
> -        ctx->temp[i] = NULL;
> -    }
> -    ctx->ntemp = 0;
> -
>       /* Only the first insn within a TB is allowed to cross a page boundary. */
>       if (ctx->base.is_jmp == DISAS_NEXT) {
>           if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 2ad5716312..5024e6ecab 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -52,7 +52,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
>       decode_save_opc(ctx);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
>       if (a->imm) {
> -        TCGv temp = temp_new(ctx);
> +        TCGv temp = tcg_temp_new();
>           tcg_gen_addi_tl(temp, t0, a->imm);
>           t0 = temp;
>       }