Message ID | 20230221021951.453601-12-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | target/arm: gdbstub cleanups and additions | expand |
Hi, On 2/21/23 02:19, Richard Henderson wrote: > The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK > ptrace register set. > > The original gdb feature consists of two masks, data and code, which are > used to mask out the authentication code within a pointer. Following > discussion with Luis Machado, add two more masks in order to support > pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). > > Cc: Luis Machado <luis.machado@arm.com> > Cc: Thiago Jung Bauermann <thiago.bauermann@linaro.org> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > configs/targets/aarch64-linux-user.mak | 2 +- > configs/targets/aarch64-softmmu.mak | 2 +- > configs/targets/aarch64_be-linux-user.mak | 2 +- > target/arm/internals.h | 2 ++ > target/arm/gdbstub.c | 5 ++++ > target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ > gdb-xml/aarch64-pauth.xml | 15 ++++++++++ > 7 files changed, 59 insertions(+), 3 deletions(-) > create mode 100644 gdb-xml/aarch64-pauth.xml > > diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak > index db552f1839..ba8bc5fe3f 100644 > --- a/configs/targets/aarch64-linux-user.mak > +++ b/configs/targets/aarch64-linux-user.mak > @@ -1,6 +1,6 @@ > TARGET_ARCH=aarch64 > TARGET_BASE_ARCH=arm > -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml > +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml > TARGET_HAS_BFLT=y > CONFIG_SEMIHOSTING=y > CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak > index d489e6da83..b4338e9568 100644 > --- a/configs/targets/aarch64-softmmu.mak > +++ b/configs/targets/aarch64-softmmu.mak > @@ -1,5 +1,5 @@ > TARGET_ARCH=aarch64 > TARGET_BASE_ARCH=arm > TARGET_SUPPORTS_MTTCG=y > -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml > +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml > TARGET_NEED_FDT=y > diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak > index dc78044fb1..acb5620cdb 100644 > --- a/configs/targets/aarch64_be-linux-user.mak > +++ b/configs/targets/aarch64_be-linux-user.mak > @@ -1,7 +1,7 @@ > TARGET_ARCH=aarch64 > TARGET_BASE_ARCH=arm > TARGET_BIG_ENDIAN=y > -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml > +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml > TARGET_HAS_BFLT=y > CONFIG_SEMIHOSTING=y > CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 370655061e..fb88b16579 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -1331,6 +1331,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); > int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); > int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); > int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); > +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); > +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); > void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); > void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); > void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); > diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > index bf8aff7824..062c8d447a 100644 > --- a/target/arm/gdbstub.c > +++ b/target/arm/gdbstub.c > @@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) > aarch64_gdb_set_fpu_reg, > 34, "aarch64-fpu.xml", 0); > } > + if (isar_feature_aa64_pauth(&cpu->isar)) { > + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, > + aarch64_gdb_set_pauth_reg, > + 4, "aarch64-pauth.xml", 0); > + } > #endif > } else { > if (arm_feature(env, ARM_FEATURE_NEON)) { > diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c > index 3d9e9e97c8..3bee892fb7 100644 > --- a/target/arm/gdbstub64.c > +++ b/target/arm/gdbstub64.c > @@ -210,6 +210,40 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) > return 0; > } > > +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) > +{ > + switch (reg) { > + case 0: /* pauth_dmask */ > + case 1: /* pauth_cmask */ > + case 2: /* pauth_dmask_high */ > + case 3: /* pauth_cmask_high */ > + /* > + * Note that older versions of this feature only contained > + * pauth_{d,c}mask, for use with Linux user processes, and > + * thus exclusively in the low half of the address space. > + * > + * To support system mode, and to debug kernels, two new regs > + * were added to cover the high half of the address space. > + * For the purpose of pauth_ptr_mask, we can use any well-formed > + * address within the address space half -- here, 0 and -1. > + */ > + { > + bool is_data = !(reg & 1); > + bool is_high = reg & 2; > + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); > + return gdb_get_reg64(buf, mask); > + } > + default: > + return 0; > + } > +} > + > +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) > +{ > + /* All pseudo registers are read-only. */ > + return 0; > +} > + > static void output_vector_union_type(GString *s, int reg_width, > const char *name) > { > diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml > new file mode 100644 > index 0000000000..24af5f903c > --- /dev/null > +++ b/gdb-xml/aarch64-pauth.xml > @@ -0,0 +1,15 @@ > +<?xml version="1.0"?> > +<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc. > + > + Copying and distribution of this file, with or without modification, > + are permitted in any medium without royalty provided the copyright > + notice and this notice are preserved. --> > + > +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> > +<feature name="org.gnu.gdb.aarch64.pauth"> > + <reg name="pauth_dmask" bitsize="64"/> > + <reg name="pauth_cmask" bitsize="64"/> > + <reg name="pauth_dmask_high" bitsize="64"/> > + <reg name="pauth_cmask_high" bitsize="64"/> > +</feature> > + FTR, I've pushed the gdb-side changes: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6d0020873deb2f2c4e0965dc2ebf227bc1db3140 IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. 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On Tue, 21 Feb 2023 at 02:21, Richard Henderson <richard.henderson@linaro.org> wrote: > > The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK > ptrace register set. > > The original gdb feature consists of two masks, data and code, which are > used to mask out the authentication code within a pointer. Following > discussion with Luis Machado, add two more masks in order to support > pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). > > Cc: Luis Machado <luis.machado@arm.com> > Cc: Thiago Jung Bauermann <thiago.bauermann@linaro.org> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index db552f1839..ba8bc5fe3f 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index d489e6da83..b4338e9568 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml TARGET_NEED_FDT=y diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dc78044fb1..acb5620cdb 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_BIG_ENDIAN=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/internals.h b/target/arm/internals.h index 370655061e..fb88b16579 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1331,6 +1331,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index bf8aff7824..062c8d447a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } + if (isar_feature_aa64_pauth(&cpu->isar)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, + aarch64_gdb_set_pauth_reg, + 4, "aarch64-pauth.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3d9e9e97c8..3bee892fb7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,6 +210,40 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: /* pauth_dmask */ + case 1: /* pauth_cmask */ + case 2: /* pauth_dmask_high */ + case 3: /* pauth_cmask_high */ + /* + * Note that older versions of this feature only contained + * pauth_{d,c}mask, for use with Linux user processes, and + * thus exclusively in the low half of the address space. + * + * To support system mode, and to debug kernels, two new regs + * were added to cover the high half of the address space. + * For the purpose of pauth_ptr_mask, we can use any well-formed + * address within the address space half -- here, 0 and -1. + */ + { + bool is_data = !(reg & 1); + bool is_high = reg & 2; + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); + return gdb_get_reg64(buf, mask); + } + default: + return 0; + } +} + +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* All pseudo registers are read-only. */ + return 0; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml new file mode 100644 index 0000000000..24af5f903c --- /dev/null +++ b/gdb-xml/aarch64-pauth.xml @@ -0,0 +1,15 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.aarch64.pauth"> + <reg name="pauth_dmask" bitsize="64"/> + <reg name="pauth_cmask" bitsize="64"/> + <reg name="pauth_dmask_high" bitsize="64"/> + <reg name="pauth_cmask_high" bitsize="64"/> +</feature> +
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Cc: Luis Machado <luis.machado@arm.com> Cc: Thiago Jung Bauermann <thiago.bauermann@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- target/arm/internals.h | 2 ++ target/arm/gdbstub.c | 5 ++++ target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ gdb-xml/aarch64-pauth.xml | 15 ++++++++++ 7 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/aarch64-pauth.xml