| Message ID | 20230214155715.451130-1-brgl@bgdev.pl |
|---|---|
| Headers | show |
| Series | arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs | expand |
On Wed, Feb 15, 2023 at 8:06 AM Shazad Hussain <quic_shazhuss@quicinc.com> wrote: > > > > On 2/14/2023 9:27 PM, Bartosz Golaszewski wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > > > This enables the QUPv3 interfaces that are exposed on the sa8775p-ride > > board: I2C, SPI and the GNSS UART. > > > > Bartosz Golaszewski (3): > > arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride > > arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride > > arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for > > Hi Bartosz, > This instance is for BT HS UART , not for GNSS. > For GNSS we have uart12 (0x00A94000). > Thanks, I'll rectify it in v2. Bart
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> This enables the QUPv3 interfaces that are exposed on the sa8775p-ride board: I2C, SPI and the GNSS UART. Bartosz Golaszewski (3): arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 67 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 72 +++++++++++++++++++++++ 2 files changed, 139 insertions(+)