| Message ID | 20230207-topic-sm8550-upstream-bam-dma-bindings-fix-v1-1-57dba71e8727@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: dma: qcom,bam-dma: add optional memory interconnect properties | expand |
On 07/02/2023 11:32, Dmitry Baryshkov wrote: > On 07/02/2023 12:03, Neil Armstrong wrote: >> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >> in order to have functional DMA. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) > > I suspect this will not work without a change for a driver. > I had the impression single interconnect entries would be taken in account by the platform core, but it doesn't seem to be the case, anyway I can;t find any code doing that. I'll resend with a driver change. Neil
On 07/02/2023 16:27, Dmitry Baryshkov wrote: > On 07/02/2023 15:35, Neil Armstrong wrote: >> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>> in order to have functional DMA. >>>> >>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>> --- >>>> Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>> >>> I suspect this will not work without a change for a driver. >>> >> >> I had the impression single interconnect entries would be taken in account >> by the platform core, but it doesn't seem to be the case, anyway I can;t >> find >> any code doing that. > > Probably you mixed interconnects and power-domains here. > The driver change was submitted some time ago: https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/ There is already DTS user of it and we expect driver to be resubmitted at some point. What I don't really get is that crypto driver sets bandwidth for interconnects, not the BAM. Why BAM needs interconnect? Usually you do not need to initialize some middle paths. Getting the final interconnect path (e.g. crypto-memory) is enough, because it includes everything in between. Maybe my review tag was a bit premature... Best regards, Krzysztof
On 2/8/23 2:38 PM, neil.armstrong@linaro.org wrote: > On 08/02/2023 10:03, Krzysztof Kozlowski wrote: >> On 07/02/2023 16:27, Dmitry Baryshkov wrote: >>> On 07/02/2023 15:35, Neil Armstrong wrote: >>>> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>>>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>>>> in order to have functional DMA. >>>>>> >>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>>>> --- >>>>>> Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>>>> 1 file changed, 6 insertions(+) >>>>> >>>>> I suspect this will not work without a change for a driver. >>>>> >>>> >>>> I had the impression single interconnect entries would be taken in >>>> account >>>> by the platform core, but it doesn't seem to be the case, anyway I >>>> can;t >>>> find >>>> any code doing that. >>> >>> Probably you mixed interconnects and power-domains here. >>> >> >> The driver change was submitted some time ago: >> https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/ >> >> There is already DTS user of it and we expect driver to be resubmitted >> at some point. >> >> What I don't really get is that crypto driver sets bandwidth for >> interconnects, not the BAM. Why BAM needs interconnect? Usually you do >> not need to initialize some middle paths. Getting the final interconnect >> path (e.g. crypto-memory) is enough, because it includes everything in >> between. > > Indeed the interconnect on BAM may be redundant since QCE sets the BW, > I'll investigate to understand if it's also necessary on BAM. Since we are already doing this via QCE driver (since crypto block on qcom SoCs employs BAM DMA services) via [1], this change is not needed for sm8150, sm8250, sm8350 and subsequent qcom SoCs (available presently), so this patch can be dropped. [1]. https://www.spinics.net/lists/linux-arm-msm/msg142957.html Thanks, Bhupesh
On 09/02/2023 09:25, Bhupesh Sharma wrote: > On 2/8/23 2:38 PM, neil.armstrong@linaro.org wrote: >> On 08/02/2023 10:03, Krzysztof Kozlowski wrote: >>> On 07/02/2023 16:27, Dmitry Baryshkov wrote: >>>> On 07/02/2023 15:35, Neil Armstrong wrote: >>>>> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>>>>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>>>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>>>>> in order to have functional DMA. >>>>>>> >>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>>>>> --- >>>>>>> Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>>>>> 1 file changed, 6 insertions(+) >>>>>> >>>>>> I suspect this will not work without a change for a driver. >>>>>> >>>>> >>>>> I had the impression single interconnect entries would be taken in account >>>>> by the platform core, but it doesn't seem to be the case, anyway I can;t >>>>> find >>>>> any code doing that. >>>> >>>> Probably you mixed interconnects and power-domains here. >>>> >>> >>> The driver change was submitted some time ago: >>> https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/ >>> >>> There is already DTS user of it and we expect driver to be resubmitted >>> at some point. >>> >>> What I don't really get is that crypto driver sets bandwidth for >>> interconnects, not the BAM. Why BAM needs interconnect? Usually you do >>> not need to initialize some middle paths. Getting the final interconnect >>> path (e.g. crypto-memory) is enough, because it includes everything in >>> between. >> >> Indeed the interconnect on BAM may be redundant since QCE sets the BW, >> I'll investigate to understand if it's also necessary on BAM. > > Since we are already doing this via QCE driver (since crypto block on qcom SoCs employs BAM DMA services) via [1], this change is not needed for sm8150, sm8250, sm8350 and subsequent qcom SoCs (available presently), so this patch can be dropped. Ack, I'll push a patch to remove the interconnect properties from the BAM node in sm8550. Neil > > [1]. https://www.spinics.net/lists/linux-arm-msm/msg142957.html > > Thanks, > Bhupesh
On 09-02-23, 13:55, Bhupesh Sharma wrote: > On 2/8/23 2:38 PM, neil.armstrong@linaro.org wrote: > > On 08/02/2023 10:03, Krzysztof Kozlowski wrote: > > > What I don't really get is that crypto driver sets bandwidth for > > > interconnects, not the BAM. Why BAM needs interconnect? Usually you do > > > not need to initialize some middle paths. Getting the final interconnect > > > path (e.g. crypto-memory) is enough, because it includes everything in > > > between. > > > > Indeed the interconnect on BAM may be redundant since QCE sets the BW, > > I'll investigate to understand if it's also necessary on BAM. > > Since we are already doing this via QCE driver (since crypto block on qcom > SoCs employs BAM DMA services) via [1], this change is not needed for > sm8150, sm8250, sm8350 and subsequent qcom SoCs (available presently), so > this patch can be dropped. Is that the right approach, should the dma consumers request the bandwidth or the dma driver. I am kind of leaning on the former
diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 003098caf709..e922fafca833 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -36,6 +36,12 @@ properties: interrupts: maxItems: 1 + interconnects: + description: Path leading to system memory + + interconnect-names: + const: memory + iommus: minItems: 1 maxItems: 4
Recents SoCs like the SM8450 or SM8550 requires memory interconnect in order to have functional DMA. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ 1 file changed, 6 insertions(+) --- base-commit: 49a8133221c71b935f36a7c340c0271c2a9ee2db change-id: 20230207-topic-sm8550-upstream-bam-dma-bindings-fix-81929c3bea5c Best regards,