| Message ID | 20230203164854.390080-3-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | 3c90b1ba8cc49b3c485e4477b9977e52a16509d3 |
| Headers | show |
| Series | [1/5] dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: correct GPIO name pattern | expand |
On Fri, 03 Feb 2023 17:48:52 +0100, Krzysztof Kozlowski wrote: > The SM8450 LPASS pin controller has GPIOs 0-22, so narrow the pattern of > possible GPIO names. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
On Fri, 3 Feb 2023 17:48:52 +0100, Krzysztof Kozlowski wrote: > The SM8450 LPASS pin controller has GPIOs 0-22, so narrow the pattern of > possible GPIO names. > > Applied, thanks! [3/5] dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: correct GPIO name pattern https://git.kernel.org/krzk/linux-dt/c/315dffb843f75cec4458714f4d151d5775e797de Best regards,
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index e04d094d1946..8bf51df0b231 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-9]|[1-2][0-9])$" + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
The SM8450 LPASS pin controller has GPIOs 0-22, so narrow the pattern of possible GPIO names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)