| Message ID | 20230124000027.3565716-11-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement FEAT_RME | expand |
On Tue, 24 Jan 2023 at 00:01, Richard Henderson <richard.henderson@linaro.org> wrote: > > With FEAT_RME, there are four physical address spaces. > For now, just define the symbols, and mention them in > the same spots as the other Phys indexes in ptw.c. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu-param.h | 2 +- > target/arm/cpu.h | 17 +++++++++++++++-- > target/arm/ptw.c | 10 ++++++++-- > 3 files changed, 24 insertions(+), 5 deletions(-) > > diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h > index 53cac9c89b..8dfd7a0bb6 100644 > --- a/target/arm/cpu-param.h > +++ b/target/arm/cpu-param.h > @@ -47,6 +47,6 @@ > bool guarded; > #endif > > -#define NB_MMU_MODES 12 > +#define NB_MMU_MODES 14 > > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 0114e1ed87..21b9afb773 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3067,8 +3067,10 @@ typedef enum ARMMMUIdx { > ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, > > /* TLBs with 1-1 mapping to the physical address spaces. */ > - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, > - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, > > /* > * These are not allocated TLBs and are used only for AT system > @@ -3132,6 +3134,17 @@ typedef enum ARMASIdx { > ARMASIdx_TagS = 3, > } ARMASIdx; > > +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) > +{ > + return ARMMMUIdx_Phys_S + space; Compile-time asserts that the mmu idxes are in the same order as the ARMSecuritySpace enum values, since we're assuming that here? Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 53cac9c89b..8dfd7a0bb6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -47,6 +47,6 @@ bool guarded; #endif -#define NB_MMU_MODES 12 +#define NB_MMU_MODES 14 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0114e1ed87..21b9afb773 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3067,8 +3067,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -3132,6 +3134,17 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 59cf64d0a6..49b8895a4e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; @@ -2632,8 +2634,10 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; default: @@ -2830,6 +2834,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi);
With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 17 +++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 3 files changed, 24 insertions(+), 5 deletions(-)