| Message ID | 20230127092126.318268-3-benjamin.gaignard@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | media: verisilicon: HEVC: fix 10bits handling | expand |
On Fri, Jan 27 2023 at 10:21:26 AM +0100, Benjamin Gaignard <benjamin.gaignard@collabora.com> wrote: > When decoding a 10bits bitstreams HEVC driver should only expose > 10bits pixel formats. > To fulfill this requirement it is needed to call > hantro_reset_raw_fmt() > when bit depth change and to correctly set match_depth in pixel > formats > enumeration. > > Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> > --- > version 5: > - Add Review and Fixes tags > > .../media/platform/verisilicon/hantro_drv.c | 44 > +++++++++++++++---- > .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + > 2 files changed, 38 insertions(+), 8 deletions(-) > > diff --git a/drivers/media/platform/verisilicon/hantro_drv.c > b/drivers/media/platform/verisilicon/hantro_drv.c > index 8cb4a68c9119..a736050fef5a 100644 > --- a/drivers/media/platform/verisilicon/hantro_drv.c > +++ b/drivers/media/platform/verisilicon/hantro_drv.c > @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, > struct vb2_queue *dst_vq) > > static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > { > - struct hantro_ctx *ctx; > - > - ctx = container_of(ctrl->handler, > - struct hantro_ctx, ctrl_handler); > - > if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { > const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; > > @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 > != 2) > /* Only 8-bit and 10-bit are supported */ > return -EINVAL; > - > - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; I think we need to make this change in a separate patch, so we can clarify the reason using s_ctrl instead of try_ctrl. Thanks! Ezequiel > } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { > const struct v4l2_ctrl_vp9_frame *dec_params = > ctrl->p_new.p_vp9_frame; > > @@ -286,6 +279,36 @@ static int hantro_try_ctrl(struct v4l2_ctrl > *ctrl) > return 0; > } > > +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct hantro_ctx *ctx; > + > + ctx = container_of(ctrl->handler, > + struct hantro_ctx, ctrl_handler); > + > + switch (ctrl->id) { > + case V4L2_CID_STATELESS_HEVC_SPS: > + { > + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; > + int bit_depth = sps->bit_depth_luma_minus8 + 8; > + int ret; > + > + if (ctx->bit_depth == bit_depth) > + return 0; > + > + ret = hantro_reset_raw_fmt(ctx, bit_depth); > + if (!ret) > + ctx->bit_depth = bit_depth; > + > + return ret; > + } > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) > { > struct hantro_ctx *ctx; > @@ -328,6 +351,11 @@ static const struct v4l2_ctrl_ops > hantro_ctrl_ops = { > .try_ctrl = hantro_try_ctrl, > }; > > +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { > + .s_ctrl = hantro_hevc_s_ctrl, > + .try_ctrl = hantro_try_ctrl, > +}; > + > static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { > .s_ctrl = hantro_jpeg_s_ctrl, > }; > @@ -470,7 +498,7 @@ static const struct hantro_ctrl controls[] = { > .codec = HANTRO_HEVC_DECODER, > .cfg = { > .id = V4L2_CID_STATELESS_HEVC_SPS, > - .ops = &hantro_ctrl_ops, > + .ops = &hantro_hevc_ctrl_ops, > }, > }, { > .codec = HANTRO_HEVC_DECODER, > diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > index b390228fd3b4..f850d8bddef6 100644 > --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > @@ -152,6 +152,7 @@ static const struct hantro_fmt > imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_NV12, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > @@ -165,6 +166,7 @@ static const struct hantro_fmt > imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_P010, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > -- > 2.34.1 >
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..a736050fef5a 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) { - struct hantro_ctx *ctx; - - ctx = container_of(ctrl->handler, - struct hantro_ctx, ctrl_handler); - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -286,6 +279,36 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + { + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + int ret; + + if (ctx->bit_depth == bit_depth) + return 0; + + ret = hantro_reset_raw_fmt(ctx, bit_depth); + if (!ret) + ctx->bit_depth = bit_depth; + + return ret; + } + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +351,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .s_ctrl = hantro_hevc_s_ctrl, + .try_ctrl = hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { .s_ctrl = hantro_jpeg_s_ctrl, }; @@ -470,7 +498,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,
When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> --- version 5: - Add Review and Fixes tags .../media/platform/verisilicon/hantro_drv.c | 44 +++++++++++++++---- .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + 2 files changed, 38 insertions(+), 8 deletions(-)