| Message ID | 20230130182459.3309057-1-peter.maydell@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Implement FEAT_FGT fine-grained traps | expand |
Hi, On Mon, Jan 30, 2023 at 6:26 PM Peter Maydell <peter.maydell@linaro.org> wrote: > > This series implements the FEAT_FGT fine-grained traps architectural > feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2, > HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable > trapping of system register and system instruction accesses on a > fine-grained basis (typically one or a few sysregs at a time). > > Changes v1->v2: > * patch 6 updated to use RTH's suggestion of doing the check > inline rather than in a helper function > * all other patches are already reviewed > > In theory we could implement this with our existing ARMCPRegInfo::accessfn > machinery, but we would end up with many many very nearly identical > access functions. Instead this series adds a new ARMCPRegInfo::fgt > field, which specifies which bit in which FGT register should be > checked; this is then tested by code in the access_check_cp_reg > helper function. > > A few bits in HFGITR_EL2 allow trapping of instructions which aren't > handled by the ARMCPRegInfo mechanism: ERET and SVC. These we just > implement "by hand". FEAT_FGT also adds new MDCR_EL3.TDCC and > MDCR_EL2.TDCC bits for trapping the Debug Comms Channel registers; > these we implement with a standard accessfn. > > The first seven patches are various cleanups and bugfixes that > I noticed while I was doing the FEAT_FGT work. In particular, we > weren't getting the priority of HSTR_EL2 traps right -- these should > take priority over UNDEF-at-EL traps but not over UNDEF-at-EL0 traps. > The rest of the series is FEAT_FGT itself. Thanks for this. I'd tested v1, which allowed me to run KVM/SME tests with qemu (which require FGTs). Reran the tests with V2: Tested-by: Fuad Tabba <tabba@google.com> Cheers, /fuad > thanks > -- PMM > > Peter Maydell (23): > target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly > target/arm: Correct syndrome for ATS12NSO* at Secure EL1 > target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} > target/arm: Move do_coproc_insn() syndrome calculation earlier > target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps > target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 > target/arm: Disable HSTR_EL2 traps if EL2 is not enabled > target/arm: Define the FEAT_FGT registers > target/arm: Implement FGT trapping infrastructure > target/arm: Mark up sysregs for HFGRTR bits 0..11 > target/arm: Mark up sysregs for HFGRTR bits 12..23 > target/arm: Mark up sysregs for HFGRTR bits 24..35 > target/arm: Mark up sysregs for HFGRTR bits 36..63 > target/arm: Mark up sysregs for HDFGRTR bits 0..11 > target/arm: Mark up sysregs for HDFGRTR bits 12..63 > target/arm: Mark up sysregs for HFGITR bits 0..11 > target/arm: Mark up sysregs for HFGITR bits 12..17 > target/arm: Mark up sysregs for HFGITR bits 18..47 > target/arm: Mark up sysregs for HFGITR bits 48..63 > target/arm: Implement the HFGITR_EL2.ERET trap > target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps > target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps > target/arm: Enable FEAT_FGT on '-cpu max' > > docs/system/arm/emulation.rst | 1 + > target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++- > target/arm/cpu.h | 18 ++ > target/arm/internals.h | 20 ++ > target/arm/syndrome.h | 10 + > target/arm/translate.h | 6 + > hw/intc/arm_gicv3_cpuif.c | 2 + > target/arm/cpu64.c | 1 + > target/arm/debug_helper.c | 46 +++- > target/arm/helper.c | 245 ++++++++++++++++- > target/arm/op_helper.c | 58 +++- > target/arm/translate-a64.c | 22 +- > target/arm/translate.c | 125 +++++---- > 13 files changed, 974 insertions(+), 64 deletions(-) > > -- > 2.34.1 > >
This series implements the FEAT_FGT fine-grained traps architectural feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2, HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable trapping of system register and system instruction accesses on a fine-grained basis (typically one or a few sysregs at a time). Changes v1->v2: * patch 6 updated to use RTH's suggestion of doing the check inline rather than in a helper function * all other patches are already reviewed In theory we could implement this with our existing ARMCPRegInfo::accessfn machinery, but we would end up with many many very nearly identical access functions. Instead this series adds a new ARMCPRegInfo::fgt field, which specifies which bit in which FGT register should be checked; this is then tested by code in the access_check_cp_reg helper function. A few bits in HFGITR_EL2 allow trapping of instructions which aren't handled by the ARMCPRegInfo mechanism: ERET and SVC. These we just implement "by hand". FEAT_FGT also adds new MDCR_EL3.TDCC and MDCR_EL2.TDCC bits for trapping the Debug Comms Channel registers; these we implement with a standard accessfn. The first seven patches are various cleanups and bugfixes that I noticed while I was doing the FEAT_FGT work. In particular, we weren't getting the priority of HSTR_EL2 traps right -- these should take priority over UNDEF-at-EL traps but not over UNDEF-at-EL0 traps. The rest of the series is FEAT_FGT itself. thanks -- PMM Peter Maydell (23): target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly target/arm: Correct syndrome for ATS12NSO* at Secure EL1 target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} target/arm: Move do_coproc_insn() syndrome calculation earlier target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 target/arm: Disable HSTR_EL2 traps if EL2 is not enabled target/arm: Define the FEAT_FGT registers target/arm: Implement FGT trapping infrastructure target/arm: Mark up sysregs for HFGRTR bits 0..11 target/arm: Mark up sysregs for HFGRTR bits 12..23 target/arm: Mark up sysregs for HFGRTR bits 24..35 target/arm: Mark up sysregs for HFGRTR bits 36..63 target/arm: Mark up sysregs for HDFGRTR bits 0..11 target/arm: Mark up sysregs for HDFGRTR bits 12..63 target/arm: Mark up sysregs for HFGITR bits 0..11 target/arm: Mark up sysregs for HFGITR bits 12..17 target/arm: Mark up sysregs for HFGITR bits 18..47 target/arm: Mark up sysregs for HFGITR bits 48..63 target/arm: Implement the HFGITR_EL2.ERET trap target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps target/arm: Enable FEAT_FGT on '-cpu max' docs/system/arm/emulation.rst | 1 + target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++- target/arm/cpu.h | 18 ++ target/arm/internals.h | 20 ++ target/arm/syndrome.h | 10 + target/arm/translate.h | 6 + hw/intc/arm_gicv3_cpuif.c | 2 + target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 46 +++- target/arm/helper.c | 245 ++++++++++++++++- target/arm/op_helper.c | 58 +++- target/arm/translate-a64.c | 22 +- target/arm/translate.c | 125 +++++---- 13 files changed, 974 insertions(+), 64 deletions(-)