| Message ID | 20230115151447.1353428-1-matthew.gerlach@linux.intel.com |
|---|---|
| Headers | show |
| Series | Enhance definition of DFH and use enhancements for UART driver | expand |
On 2023-01-15 16:14, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Add a Device Feature List (DFL) bus driver for the Altera > 16550 implementation of UART. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Marco Pagani <marpagan@redhat.com> > --- > v11: sizeof(u64) -> sizeof(*pval) > 16650 -> 16550 > > v10: track change to dfh_find_param() > > v9: add Rb Andy Shevchenko > move dfh_get_u64_param_vals to static version of dfh_get_u64_param_val > > v8: use dfh_get_u64_param_vals() > > v7: no change > > v6: move driver specific parameter definitions to limit scope > > v5: removed unneeded blank line > removed unneeded includes > included device.h and types.h > removed unneeded local variable > remove calls to dev_dbg > memset -> { } > remove space after period > explicitly include used headers > remove redundant Inc from Copyright > fix format specifier > > v4: use dev_err_probe() everywhere that is appropriate > clean up noise > change error messages to use the word, unsupported > tried again to sort Makefile and KConfig better > reorder probe function for easier error handling > use new dfh_find_param API > > v3: use passed in location of registers > use cleaned up functions for parsing parameters > > v2: clean up error messages > alphabetize header files > fix 'missing prototype' error by making function static > tried to sort Makefile and Kconfig better > --- > drivers/tty/serial/8250/8250_dfl.c | 167 +++++++++++++++++++++++++++++ > drivers/tty/serial/8250/Kconfig | 12 +++ > drivers/tty/serial/8250/Makefile | 1 + > 3 files changed, 180 insertions(+) > create mode 100644 drivers/tty/serial/8250/8250_dfl.c > > diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c > new file mode 100644 > index 000000000000..6c5ff019df4b > --- /dev/null > +++ b/drivers/tty/serial/8250/8250_dfl.c > @@ -0,0 +1,167 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Driver for FPGA UART > + * > + * Copyright (C) 2022 Intel Corporation. > + * > + * Authors: > + * Ananda Ravuri <ananda.ravuri@intel.com> > + * Matthew Gerlach <matthew.gerlach@linux.intel.com> > + */ > + > +#include <linux/bitfield.h> > +#include <linux/device.h> > +#include <linux/dfl.h> > +#include <linux/errno.h> > +#include <linux/ioport.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/types.h> > + > +#include <linux/serial.h> > +#include <linux/serial_8250.h> > + > +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 > +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 > + > +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 > +#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32) > +#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0) > + > +struct dfl_uart { > + int line; > +}; > + > +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval) > +{ > + size_t psize; > + u64 *p; > + > + p = dfh_find_param(dfl_dev, param_id, &psize); > + if (IS_ERR(p)) > + return PTR_ERR(p); > + > + if (psize != sizeof(*pval)) > + return -EINVAL; > + > + *pval = *p; > + > + return 0; > +} > + > +static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) > +{ > + struct device *dev = &dfl_dev->dev; > + u64 fifo_len, clk_freq, reg_layout; > + u32 reg_width; > + int ret; > + > + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq); > + if (ret) > + return dev_err_probe(dev, ret, "missing CLK_FRQ param\n"); > + > + uart->port.uartclk = clk_freq; > + > + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len); > + if (ret) > + return dev_err_probe(dev, ret, "missing FIFO_LEN param\n"); > + > + switch (fifo_len) { > + case 32: > + uart->port.type = PORT_ALTR_16550_F32; > + break; > + > + case 64: > + uart->port.type = PORT_ALTR_16550_F64; > + break; > + > + case 128: > + uart->port.type = PORT_ALTR_16550_F128; > + break; > + > + default: > + return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); > + } > + > + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); > + if (ret) > + return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n"); > + > + uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); > + reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); > + switch (reg_width) { > + case 4: > + uart->port.iotype = UPIO_MEM32; > + break; > + > + case 2: > + uart->port.iotype = UPIO_MEM16; > + break; > + > + default: > + return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width); > + > + } > + > + return 0; > +} > + > +static int dfl_uart_probe(struct dfl_device *dfl_dev) > +{ > + struct device *dev = &dfl_dev->dev; > + struct uart_8250_port uart = { }; > + struct dfl_uart *dfluart; > + int ret; > + > + uart.port.flags = UPF_IOREMAP; > + uart.port.mapbase = dfl_dev->mmio_res.start; > + uart.port.mapsize = resource_size(&dfl_dev->mmio_res); > + > + ret = dfl_uart_get_params(dfl_dev, &uart); > + if (ret < 0) > + return dev_err_probe(dev, ret, "failed uart feature walk\n"); > + > + if (dfl_dev->num_irqs == 1) > + uart.port.irq = dfl_dev->irqs[0]; > + > + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); > + if (!dfluart) > + return -ENOMEM; > + > + dfluart->line = serial8250_register_8250_port(&uart); > + if (dfluart->line < 0) > + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); > + > + dev_set_drvdata(dev, dfluart); > + > + return 0; > +} > + > +static void dfl_uart_remove(struct dfl_device *dfl_dev) > +{ > + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); > + > + serial8250_unregister_port(dfluart->line); > +} > + > +#define FME_FEATURE_ID_UART 0x24 > + > +static const struct dfl_device_id dfl_uart_ids[] = { > + { FME_ID, FME_FEATURE_ID_UART }, > + { } > +}; > +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); > + > +static struct dfl_driver dfl_uart_driver = { > + .drv = { > + .name = "dfl-uart", > + }, > + .id_table = dfl_uart_ids, > + .probe = dfl_uart_probe, > + .remove = dfl_uart_remove, > +}; > +module_dfl_driver(dfl_uart_driver); > + > +MODULE_DESCRIPTION("DFL Intel UART driver"); > +MODULE_AUTHOR("Intel Corporation"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig > index b0f62345bc84..020ef532940d 100644 > --- a/drivers/tty/serial/8250/Kconfig > +++ b/drivers/tty/serial/8250/Kconfig > @@ -370,6 +370,18 @@ config SERIAL_8250_FSL > erratum for Freescale 16550 UARTs in the 8250 driver. It also > enables support for ACPI enumeration. > > +config SERIAL_8250_DFL > + tristate "DFL bus driver for Altera 16550 UART" > + depends on SERIAL_8250 && FPGA_DFL > + help > + This option enables support for a Device Feature List (DFL) bus > + driver for the Altera 16550 UART. One or more Altera 16550 UARTs > + can be instantiated in a FPGA and then be discovered during > + enumeration of the DFL bus. > + > + To compile this driver as a module, chose M here: the > + module will be called 8250_dfl. > + > config SERIAL_8250_DW > tristate "Support for Synopsys DesignWare 8250 quirks" > depends on SERIAL_8250 > diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile > index 1615bfdde2a0..4e1a32812683 100644 > --- a/drivers/tty/serial/8250/Makefile > +++ b/drivers/tty/serial/8250/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o > obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o > obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o > obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o > +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o > obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o > obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o > obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o
On Mon, 16 Jan 2023, Marco Pagani wrote: > > On 2023-01-15 16:14, matthew.gerlach@linux.intel.com wrote: >> From: Matthew Gerlach <matthew.gerlach@linux.intel.com> >> >> Add a Device Feature List (DFL) bus driver for the Altera >> 16550 implementation of UART. >> >> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> >> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> >> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Reviewed-by: Marco Pagani <marpagan@redhat.com> Thanks for the review, Matthew Gerlach > >> --- >> v11: sizeof(u64) -> sizeof(*pval) >> 16650 -> 16550 >> >> v10: track change to dfh_find_param() >> >> v9: add Rb Andy Shevchenko >> move dfh_get_u64_param_vals to static version of dfh_get_u64_param_val >> >> v8: use dfh_get_u64_param_vals() >> >> v7: no change >> >> v6: move driver specific parameter definitions to limit scope >> >> v5: removed unneeded blank line >> removed unneeded includes >> included device.h and types.h >> removed unneeded local variable >> remove calls to dev_dbg >> memset -> { } >> remove space after period >> explicitly include used headers >> remove redundant Inc from Copyright >> fix format specifier >> >> v4: use dev_err_probe() everywhere that is appropriate >> clean up noise >> change error messages to use the word, unsupported >> tried again to sort Makefile and KConfig better >> reorder probe function for easier error handling >> use new dfh_find_param API >> >> v3: use passed in location of registers >> use cleaned up functions for parsing parameters >> >> v2: clean up error messages >> alphabetize header files >> fix 'missing prototype' error by making function static >> tried to sort Makefile and Kconfig better >> --- >> drivers/tty/serial/8250/8250_dfl.c | 167 +++++++++++++++++++++++++++++ >> drivers/tty/serial/8250/Kconfig | 12 +++ >> drivers/tty/serial/8250/Makefile | 1 + >> 3 files changed, 180 insertions(+) >> create mode 100644 drivers/tty/serial/8250/8250_dfl.c >> >> diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c >> new file mode 100644 >> index 000000000000..6c5ff019df4b >> --- /dev/null >> +++ b/drivers/tty/serial/8250/8250_dfl.c >> @@ -0,0 +1,167 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Driver for FPGA UART >> + * >> + * Copyright (C) 2022 Intel Corporation. >> + * >> + * Authors: >> + * Ananda Ravuri <ananda.ravuri@intel.com> >> + * Matthew Gerlach <matthew.gerlach@linux.intel.com> >> + */ >> + >> +#include <linux/bitfield.h> >> +#include <linux/device.h> >> +#include <linux/dfl.h> >> +#include <linux/errno.h> >> +#include <linux/ioport.h> >> +#include <linux/module.h> >> +#include <linux/mod_devicetable.h> >> +#include <linux/types.h> >> + >> +#include <linux/serial.h> >> +#include <linux/serial_8250.h> >> + >> +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 >> +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 >> + >> +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 >> +#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32) >> +#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0) >> + >> +struct dfl_uart { >> + int line; >> +}; >> + >> +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval) >> +{ >> + size_t psize; >> + u64 *p; >> + >> + p = dfh_find_param(dfl_dev, param_id, &psize); >> + if (IS_ERR(p)) >> + return PTR_ERR(p); >> + >> + if (psize != sizeof(*pval)) >> + return -EINVAL; >> + >> + *pval = *p; >> + >> + return 0; >> +} >> + >> +static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) >> +{ >> + struct device *dev = &dfl_dev->dev; >> + u64 fifo_len, clk_freq, reg_layout; >> + u32 reg_width; >> + int ret; >> + >> + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq); >> + if (ret) >> + return dev_err_probe(dev, ret, "missing CLK_FRQ param\n"); >> + >> + uart->port.uartclk = clk_freq; >> + >> + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len); >> + if (ret) >> + return dev_err_probe(dev, ret, "missing FIFO_LEN param\n"); >> + >> + switch (fifo_len) { >> + case 32: >> + uart->port.type = PORT_ALTR_16550_F32; >> + break; >> + >> + case 64: >> + uart->port.type = PORT_ALTR_16550_F64; >> + break; >> + >> + case 128: >> + uart->port.type = PORT_ALTR_16550_F128; >> + break; >> + >> + default: >> + return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); >> + } >> + >> + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); >> + if (ret) >> + return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n"); >> + >> + uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); >> + reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); >> + switch (reg_width) { >> + case 4: >> + uart->port.iotype = UPIO_MEM32; >> + break; >> + >> + case 2: >> + uart->port.iotype = UPIO_MEM16; >> + break; >> + >> + default: >> + return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width); >> + >> + } >> + >> + return 0; >> +} >> + >> +static int dfl_uart_probe(struct dfl_device *dfl_dev) >> +{ >> + struct device *dev = &dfl_dev->dev; >> + struct uart_8250_port uart = { }; >> + struct dfl_uart *dfluart; >> + int ret; >> + >> + uart.port.flags = UPF_IOREMAP; >> + uart.port.mapbase = dfl_dev->mmio_res.start; >> + uart.port.mapsize = resource_size(&dfl_dev->mmio_res); >> + >> + ret = dfl_uart_get_params(dfl_dev, &uart); >> + if (ret < 0) >> + return dev_err_probe(dev, ret, "failed uart feature walk\n"); >> + >> + if (dfl_dev->num_irqs == 1) >> + uart.port.irq = dfl_dev->irqs[0]; >> + >> + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); >> + if (!dfluart) >> + return -ENOMEM; >> + >> + dfluart->line = serial8250_register_8250_port(&uart); >> + if (dfluart->line < 0) >> + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); >> + >> + dev_set_drvdata(dev, dfluart); >> + >> + return 0; >> +} >> + >> +static void dfl_uart_remove(struct dfl_device *dfl_dev) >> +{ >> + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); >> + >> + serial8250_unregister_port(dfluart->line); >> +} >> + >> +#define FME_FEATURE_ID_UART 0x24 >> + >> +static const struct dfl_device_id dfl_uart_ids[] = { >> + { FME_ID, FME_FEATURE_ID_UART }, >> + { } >> +}; >> +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); >> + >> +static struct dfl_driver dfl_uart_driver = { >> + .drv = { >> + .name = "dfl-uart", >> + }, >> + .id_table = dfl_uart_ids, >> + .probe = dfl_uart_probe, >> + .remove = dfl_uart_remove, >> +}; >> +module_dfl_driver(dfl_uart_driver); >> + >> +MODULE_DESCRIPTION("DFL Intel UART driver"); >> +MODULE_AUTHOR("Intel Corporation"); >> +MODULE_LICENSE("GPL"); >> diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig >> index b0f62345bc84..020ef532940d 100644 >> --- a/drivers/tty/serial/8250/Kconfig >> +++ b/drivers/tty/serial/8250/Kconfig >> @@ -370,6 +370,18 @@ config SERIAL_8250_FSL >> erratum for Freescale 16550 UARTs in the 8250 driver. It also >> enables support for ACPI enumeration. >> >> +config SERIAL_8250_DFL >> + tristate "DFL bus driver for Altera 16550 UART" >> + depends on SERIAL_8250 && FPGA_DFL >> + help >> + This option enables support for a Device Feature List (DFL) bus >> + driver for the Altera 16550 UART. One or more Altera 16550 UARTs >> + can be instantiated in a FPGA and then be discovered during >> + enumeration of the DFL bus. >> + >> + To compile this driver as a module, chose M here: the >> + module will be called 8250_dfl. >> + >> config SERIAL_8250_DW >> tristate "Support for Synopsys DesignWare 8250 quirks" >> depends on SERIAL_8250 >> diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile >> index 1615bfdde2a0..4e1a32812683 100644 >> --- a/drivers/tty/serial/8250/Makefile >> +++ b/drivers/tty/serial/8250/Makefile >> @@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o >> obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o >> obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o >> obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o >> +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o >> obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o >> obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o >> obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o > >
On 2023-01-15 at 07:14:43 -0800, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > This patchset enhances the definition of the Device Feature Header (DFH) used by > the Device Feature List (DFL) bus and then uses the new enhancements in a UART > driver. > > The enhancements to the DFH includes the introduction of parameter blocks. > Like PCI capabilities, the DFH parameter blocks further describe > the hardware to software. In the case of the UART, the parameter blocks > provide information for the interrupt, clock frequency, and register layout. > > Duplication of code parsing of the parameter blocks in multiple DFL drivers > is a concern. Using swnodes was considered to help minimize parsing code > duplication, but their use did not help the problem. Furthermore the highly > changeable nature of FPGAs employing the DFL bus makes the use of swnodes > inappropriate. > > Patch 1 updates the DFL documentation to describe the added functionality to DFH. > > Patch 2 adds the definitions for DFHv1. > > Patch 3 adds basic support for DFHv1. It adds functionality to parse parameter blocks > and adds the functionality to parse the explicit location of a feature's register set. > > Patch 4 adds a DFL UART driver that makes use of the new features of DFHv1. Looks good to me and see Greg has taken this patchset. Thanks, Yilun > > Basheer Ahmed Muddebihal (1): > fpga: dfl: Add DFHv1 Register Definitions > > Matthew Gerlach (3): > Documentation: fpga: dfl: Add documentation for DFHv1 > fpga: dfl: add basic support for DFHv1 > tty: serial: 8250: add DFL bus driver for Altera 16550. > > Documentation/fpga/dfl.rst | 119 ++++++++++++++ > drivers/fpga/dfl.c | 245 +++++++++++++++++++++++------ > drivers/fpga/dfl.h | 43 +++++ > drivers/tty/serial/8250/8250_dfl.c | 167 ++++++++++++++++++++ > drivers/tty/serial/8250/Kconfig | 12 ++ > drivers/tty/serial/8250/Makefile | 1 + > include/linux/dfl.h | 8 + > 7 files changed, 544 insertions(+), 51 deletions(-) > create mode 100644 drivers/tty/serial/8250/8250_dfl.c > > -- > 2.25.1 >
From: Matthew Gerlach <matthew.gerlach@linux.intel.com> This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a UART driver. The enhancements to the DFH includes the introduction of parameter blocks. Like PCI capabilities, the DFH parameter blocks further describe the hardware to software. In the case of the UART, the parameter blocks provide information for the interrupt, clock frequency, and register layout. Duplication of code parsing of the parameter blocks in multiple DFL drivers is a concern. Using swnodes was considered to help minimize parsing code duplication, but their use did not help the problem. Furthermore the highly changeable nature of FPGAs employing the DFL bus makes the use of swnodes inappropriate. Patch 1 updates the DFL documentation to describe the added functionality to DFH. Patch 2 adds the definitions for DFHv1. Patch 3 adds basic support for DFHv1. It adds functionality to parse parameter blocks and adds the functionality to parse the explicit location of a feature's register set. Patch 4 adds a DFL UART driver that makes use of the new features of DFHv1. Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support for DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550. Documentation/fpga/dfl.rst | 119 ++++++++++++++ drivers/fpga/dfl.c | 245 +++++++++++++++++++++++------ drivers/fpga/dfl.h | 43 +++++ drivers/tty/serial/8250/8250_dfl.c | 167 ++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 8 + 7 files changed, 544 insertions(+), 51 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c