| Message ID | 20230117225824.1552604-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | clk: qcom: msm8996: add support for the CBF clock | expand |
On 17.01.2023 23:58, Dmitry Baryshkov wrote: > The vendor kernel uses RPM_SMD_XO_CLK_SRC clock as an CXO clock rather > than using the RPM_SMD_BB_CLK1 directly. Follow this example and switch > msm8996.dtsi to use RPM_SMD_XO_CLK_SRC clock instead of RPM_SMB_BB_CLK1. > > Fixes: 2b8c9c77c268 ("arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1") > Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8996.dtsi | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index a8544c4158ac..150d13c0f4b8 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -713,7 +713,7 @@ gcc: clock-controller@300000 { > #power-domain-cells = <1>; > reg = <0x00300000 0x90000>; > > - clocks = <&rpmcc RPM_SMD_BB_CLK1>, > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > <&rpmcc RPM_SMD_LN_BB_CLK>, > <&sleep_clk>, > <&pciephy_0>, > @@ -1055,7 +1055,7 @@ dsi0_phy: phy@994400 { > #clock-cells = <1>; > #phy-cells = <0>; > > - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; > + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "ref"; > status = "disabled"; > }; > @@ -1123,7 +1123,7 @@ dsi1_phy: phy@996400 { > #clock-cells = <1>; > #phy-cells = <0>; > > - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; > + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "ref"; > status = "disabled"; > }; > @@ -2952,7 +2952,7 @@ kryocc: clock-controller@6400000 { > reg = <0x06400000 0x90000>; > > clock-names = "xo", "sys_apcs_aux"; > - clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&apcs_glb>; > > #clock-cells = <1>; > }; > @@ -3071,7 +3071,7 @@ sdhc1: mmc@7464900 { > clock-names = "iface", "core", "xo"; > clocks = <&gcc GCC_SDCC1_AHB_CLK>, > <&gcc GCC_SDCC1_APPS_CLK>, > - <&rpmcc RPM_SMD_BB_CLK1>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > resets = <&gcc GCC_SDCC1_BCR>; > > pinctrl-names = "default", "sleep"; > @@ -3095,7 +3095,7 @@ sdhc2: mmc@74a4900 { > clock-names = "iface", "core", "xo"; > clocks = <&gcc GCC_SDCC2_AHB_CLK>, > <&gcc GCC_SDCC2_APPS_CLK>, > - <&rpmcc RPM_SMD_BB_CLK1>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > resets = <&gcc GCC_SDCC2_BCR>; > > pinctrl-names = "default", "sleep"; > @@ -3417,7 +3417,7 @@ adsp_pil: remoteproc@9300000 { > interrupt-names = "wdog", "fatal", "ready", > "handover", "stop-ack"; > > - clocks = <&rpmcc RPM_SMD_BB_CLK1>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "xo"; > > memory-region = <&adsp_mem>;
On 17.01.2023 23:58, Dmitry Baryshkov wrote: > Turn CBF into the interconnect provider. Scale CBF frequency (bandwidth) > according to CPU frequencies. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 50 +++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 7d8e31b84959..fc932a059d9f 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -49,6 +49,7 @@ CPU0: cpu@0 { > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > clocks = <&kryocc 0>; > + interconnects = <&cbf 0 &cbf 1>; dt-bindings entries instead of magic numbers, pretty please? The rest lgtm Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > operating-points-v2 = <&cluster0_opp>; > #cooling-cells = <2>; > next-level-cache = <&L2_0>; > @@ -66,6 +67,7 @@ CPU1: cpu@1 { > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > clocks = <&kryocc 0>; > + interconnects = <&cbf 0 &cbf 1>; > operating-points-v2 = <&cluster0_opp>; > #cooling-cells = <2>; > next-level-cache = <&L2_0>; > @@ -79,6 +81,7 @@ CPU2: cpu@100 { > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > clocks = <&kryocc 1>; > + interconnects = <&cbf 0 &cbf 1>; > operating-points-v2 = <&cluster1_opp>; > #cooling-cells = <2>; > next-level-cache = <&L2_1>; > @@ -96,6 +99,7 @@ CPU3: cpu@101 { > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > clocks = <&kryocc 1>; > + interconnects = <&cbf 0 &cbf 1>; > operating-points-v2 = <&cluster1_opp>; > #cooling-cells = <2>; > next-level-cache = <&L2_1>; > @@ -147,91 +151,109 @@ opp-307200000 { > opp-hz = /bits/ 64 <307200000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-422400000 { > opp-hz = /bits/ 64 <422400000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-480000000 { > opp-hz = /bits/ 64 <480000000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-556800000 { > opp-hz = /bits/ 64 <556800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-652800000 { > opp-hz = /bits/ 64 <652800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <384000>; > }; > opp-729600000 { > opp-hz = /bits/ 64 <729600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <460800>; > }; > opp-844800000 { > opp-hz = /bits/ 64 <844800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <537600>; > }; > opp-960000000 { > opp-hz = /bits/ 64 <960000000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <672000>; > }; > opp-1036800000 { > opp-hz = /bits/ 64 <1036800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <672000>; > }; > opp-1113600000 { > opp-hz = /bits/ 64 <1113600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <825600>; > }; > opp-1190400000 { > opp-hz = /bits/ 64 <1190400000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <825600>; > }; > opp-1228800000 { > opp-hz = /bits/ 64 <1228800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <902400>; > }; > opp-1324800000 { > opp-hz = /bits/ 64 <1324800000>; > opp-supported-hw = <0xd>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1056000>; > }; > opp-1363200000 { > opp-hz = /bits/ 64 <1363200000>; > opp-supported-hw = <0x2>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1132800>; > }; > opp-1401600000 { > opp-hz = /bits/ 64 <1401600000>; > opp-supported-hw = <0xd>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1132800>; > }; > opp-1478400000 { > opp-hz = /bits/ 64 <1478400000>; > opp-supported-hw = <0x9>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1190400>; > }; > opp-1497600000 { > opp-hz = /bits/ 64 <1497600000>; > opp-supported-hw = <0x04>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1305600>; > }; > opp-1593600000 { > opp-hz = /bits/ 64 <1593600000>; > opp-supported-hw = <0x9>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1382400>; > }; > }; > > @@ -245,136 +267,163 @@ opp-307200000 { > opp-hz = /bits/ 64 <307200000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-403200000 { > opp-hz = /bits/ 64 <403200000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-480000000 { > opp-hz = /bits/ 64 <480000000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-556800000 { > opp-hz = /bits/ 64 <556800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-652800000 { > opp-hz = /bits/ 64 <652800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-729600000 { > opp-hz = /bits/ 64 <729600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <307200>; > }; > opp-806400000 { > opp-hz = /bits/ 64 <806400000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <384000>; > }; > opp-883200000 { > opp-hz = /bits/ 64 <883200000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <460800>; > }; > opp-940800000 { > opp-hz = /bits/ 64 <940800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <537600>; > }; > opp-1036800000 { > opp-hz = /bits/ 64 <1036800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <595200>; > }; > opp-1113600000 { > opp-hz = /bits/ 64 <1113600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <672000>; > }; > opp-1190400000 { > opp-hz = /bits/ 64 <1190400000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <672000>; > }; > opp-1248000000 { > opp-hz = /bits/ 64 <1248000000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <748800>; > }; > opp-1324800000 { > opp-hz = /bits/ 64 <1324800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <825600>; > }; > opp-1401600000 { > opp-hz = /bits/ 64 <1401600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <902400>; > }; > opp-1478400000 { > opp-hz = /bits/ 64 <1478400000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <979200>; > }; > opp-1555200000 { > opp-hz = /bits/ 64 <1555200000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1056000>; > }; > opp-1632000000 { > opp-hz = /bits/ 64 <1632000000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1190400>; > }; > opp-1708800000 { > opp-hz = /bits/ 64 <1708800000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1228800>; > }; > opp-1785600000 { > opp-hz = /bits/ 64 <1785600000>; > opp-supported-hw = <0xf>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1305600>; > }; > opp-1804800000 { > opp-hz = /bits/ 64 <1804800000>; > opp-supported-hw = <0xe>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1305600>; > }; > opp-1824000000 { > opp-hz = /bits/ 64 <1824000000>; > opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1382400>; > }; > opp-1900800000 { > opp-hz = /bits/ 64 <1900800000>; > opp-supported-hw = <0x4>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1305600>; > }; > opp-1920000000 { > opp-hz = /bits/ 64 <1920000000>; > opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1459200>; > }; > opp-1996800000 { > opp-hz = /bits/ 64 <1996800000>; > opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1593600>; > }; > opp-2073600000 { > opp-hz = /bits/ 64 <2073600000>; > opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1593600>; > }; > opp-2150400000 { > opp-hz = /bits/ 64 <2150400000>; > opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > + opp-peak-kBps = <1593600>; > }; > }; > > @@ -3567,6 +3616,7 @@ cbf: clock-controller@9a11000 { > reg = <0x09a11000 0x10000>; > clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&apcs_glb>; > #clock-cells = <0>; > + #interconnect-cells = <1>; > }; > > intc: interrupt-controller@9bc0000 {
On MSM8996 two CPU clusters are interconnected using the Core Bus Fabric (CBF). In order for the CPU clusters to function properly, it should be clocked following the core's frequencies to provide adequate bandwidth. On the other hand the CBF's clock rate can be used by other drivers (e.g. by the pending SPDM driver to provide input on the CPU performance). Thus register CBF as a clock (required for CPU to boot) and add a tiny interconnect layer on top of it to let cpufreq/opp scale the CBF clock. Dependencies: [1] [1] https://lore.kernel.org/linux-arm-msm/20230111191453.2509468-1-dmitry.baryshkov@linaro.org/ - Relicensed schema to GPL-2.0 + BSD-2-Clause (Krzysztof) - Changed clock driver to use parent_hws (Konrad) - Fixed indentation in CBF clock driver (Konrad) - Changed MODULE_LICENSE of CBF clock driver to GPL from GPL-v2 - Switched CBF to use RPM_SMD_XO_CLK_SRC as one of the parents - Enabled RPM_SMD_XO_CLK_SRC on msm8996 platform and switch to it from RPM_SMD_BB_CLK1 clock Dmitry Baryshkov (7): dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller clk: qcom: add msm8996 Core Bus Framework (CBF) support clk: qcom: cbf-msm8996: scale CBF clock according to the CPUfreq clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform arm64: qcom: dts: msm8996 switch from RPM_SMD_BB_CLK1 to RPM_SMD_XO_CLK_SRC arm64: dts: qcom: msm8996: add CBF device entry arm64: dts: qcom: msm8996: scale CBF clock according to the CPUfreq .../bindings/clock/qcom,msm8996-cbf.yaml | 53 ++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 71 ++- drivers/clk/qcom/Makefile | 2 +- drivers/clk/qcom/clk-cbf-8996.c | 456 ++++++++++++++++++ drivers/clk/qcom/clk-smd-rpm.c | 2 + 5 files changed, 576 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml create mode 100644 drivers/clk/qcom/clk-cbf-8996.c