| Message ID | 20230114233500.3294789-1-lars@metafoo.de |
|---|---|
| State | Accepted |
| Commit | 3ed741db04f58e8df0d46cec7ecfc4bfd075f047 |
| Headers | show |
| Series | [1/3] clk: vc5: Use `clamp()` to restrict PLL range | expand |
On 15/01/2023 00:35, Lars-Peter Clausen wrote: > The 5P49V60 clock generator is part of the same family of devices that is > described by the versaclock5 binding documentation. > > Add the compatible string of the 5P49V60 to the binding documentation. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Quoting Lars-Peter Clausen (2023-01-14 15:34:58) > The VCO frequency needs to be within a certain range and the driver > enforces this. > > Make use of the clamp macro to implement this instead of open-coding it. > This makes the code a bit shorter and also semanticly stronger. > > Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> > --- Applied to clk-next
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index e9737969170e..54fee43d6564 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -449,10 +449,7 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, u32 div_int; u64 div_frc; - if (rate < VC5_PLL_VCO_MIN) - rate = VC5_PLL_VCO_MIN; - if (rate > VC5_PLL_VCO_MAX) - rate = VC5_PLL_VCO_MAX; + rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX); /* Determine integer part, which is 12 bit wide */ div_int = rate / *parent_rate;
The VCO frequency needs to be within a certain range and the driver enforces this. Make use of the clamp macro to implement this instead of open-coding it. This makes the code a bit shorter and also semanticly stronger. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> --- drivers/clk/clk-versaclock5.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)